CSENT
SENT/SAE J2716 Controller

The CSENT core implements a controller for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and also the industry de-facto standard Short PWM Code (SPC) protocol. It can be used for conveying data from one or multiple sensors to a centralized controller using a single SENT line.

 The CSENT core can be configured as a Transmitter and/or as a Receiver, and therefore it is suitable for adding a SENT interface to devices transmitting sensor data or to controllers receiving sensor data. It provides access to its control, status, and data registers via a 32-bit APB bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation. The core allows for Transmitter operation without requiring any external programming or control. The reset values for all its control registers are defined at synthesis time, and at run time the system only needs to write sensor data to the core.

The CSENT core is suitable for designing low-cost digital automotive sensors and automotive controller units. 

The CSENT core is designed with industry best practices. The core contains no latches or tri-states, and is fully synchronous with a single clock domain. The core is available in Verilog RTL or as targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation. 

The core includes everything required for successful implementation:

  •     Source code Verilog RTL or targeted netlist
  •     Testbench
  •     Sample synthesis and simulation scripts
  •     Documentation

The CSENT can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample implementation results, which do not represent the highest speed or smallest area possible for the core and do not include the area for the implementation of the FIFOs. Please contact CAST to get characterization data for your target configuration and technology.

Configuration Target Technology Area Fmax
Tx and Rx
TSMC 28hpm
2410 um2 / 4,850 Gates
1000 MHz
Tx only
TSMC 28hpm
1152 um2 / 2,300 Gates
1000 MHz

The CSENT can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following are sample implementation results, which do not represent the highest speed or smallest area possible for the core and do not include the area for the implementation of the FIFOs. Please contact CAST to get characterization data for your target configuration and technology.

Configuration Target Technology Area Fmax
TX & RX no FIFO
StartixV / 5sgxea9n3fc5c4
570 ALMs, 693 Regs
315 MHz
TX only no FIFO
StartixV / 5sgxea9n3fc5c4
275 ALMs, 351 Regs
339 MHz
TX & RX no FIFO
CyloneV / 5ceba9f31c7
571 ALMs, 697 Regs
162 MHz
TX only no FIFO
CyloneV / 5ceba9f31c7
279 ALMs, 351 Regs
185 MHz
TX & RX no FIFO
ArriaV / 5agxbb3d4f35c4
570 ALMs, 701 Regs
204 MHz
TX only no FIFO
ArriaV / 5agxbb3d4f35c4
280 ALMs, 352 Regs
247 MHz
TX & RX no FIFO
Arria10 / 10as057k2f35i2lg
593 ALMs, 688 Regs
365 MHz
TX only no FIFO
Arria10 / 10as057k2f35i2lg
284 ALMs, 349 Regs
401 MHz

The CSENT can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following are sample implementation results, which do not represent the highest speed or smallest area possible for the core and do not include the area for the implementation of the FIFOs. Please contact CAST to get characterization data for your target configuration and technology.

Configuration Target Technology Area Fmax
TX & RX no FIFO
Kintex7 / xc7k480t-3
781 Slice LUTs, 639 Slice Regs
361 MHz
TX only no FIFO
Kintex7 / xc7k480t-3
430 Slice LUTs, 316 Slice Regs
358 MHz
TX & RX no FIFO
Artix7 / xc7a200t-3
773 Slice LUTs, 637 Slice Regs
246 MHz
TX only no FIFO
Artix7 / xc7a200t-3
401 Slice LUTs, 316 Slice Regs
247 MHz
TX & RX no FIFO
Virtex7 / xc7vx330t-3
782 Slice LUTs, 637 Slice Regs
364 MHz
TX only no FIFO
Virtex7 / xc7vx330t-3
430 Slice LUTs, 316 Slice Regs
379 MHz
TX & RX no FIFO
US Kintex / xcku035-3
766 CLB LUTs, 638 CLB Regs
460 MHz
TX only no FIFO
US Kintex / xcku035-3
405 CLB LUTs, 316 CLB Regs
427 MHz
TX & RX no FIFO
US Virtex / xcvu095-3
798 CLB LUTs, 638 CLB Regs
472 MHz
TX only no FIFO
US Virtex / xcvu095-3
407 CLB LUTs, 319 CLB Regs
446 MHz

Related Content

Features List

SENT/SAE J2716 Receiver & Transmitter

  • Fast and Slow Channel Transmit or Receive
  • CRC generation for Transmitter, and CRC checking for Receiver
  • All types of SENT Frames
    • Programmable data length (4 to 24 bits) for Fast Channel Frames
    • Short (8-bit data) and Enhanced (12- or 16-bit data) Message Formats for Slow Channel
  • Optional Pause Pulse with programmable length
  • Supports inverted SENT protocol

Short PWM Code (SPC) Receiver & Transmitter

  • Allows up to four sensors (transmitters) to use the same physical SENT connection
  • Programmable master trigger pulse length

Ease of Integration

  • 32-bit APB interface, and comprehensive set of interrupts
  • Programmable 4-bit clock divider and high precision 16-bit clock pre-scale
  • Receive and Transmit FIFO of configurable size for Fast Channel data
  • Run-time programmable configuration registers
  • Synthesis-time defined reset values for all registers, enables data transmit without control from host processor
  • LINT-clean, single-clock domain, scan-ready design

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