Silicon IP Cores
Audio
Configurable Audio Interfaces and Sample Rate Conversion
Simplify audio integration for ASIC and FPGA systems with these high-quality audio interface IP cores. Each is designed for efficient operation, minimal resource usage, straightforward integration, reliable operation, and broad application coverage, without the complexity, size, or overhead often found in alternative solutions. They include a low-risk legacy codec interface, high-fidelity sample rate conversion, and scalable serial audio I/O.
AC’97 Audio Controller (AC97-CTRL) — A compact, configurable core supporting AC’97 Rev. 2.3 with up to 10 transmit and 10 receive channels—more than typical alternatives. It includes AXI, AXI-Stream, APB, and MCU interfaces,an optional integrated DMA, and full power/reset logic. It is an efficient choice for embedded and industrial systems that need basic analog audio or low-risk legacy upgrades.
Audio Sample Rate Converter (ASRC) — Combining synchronous and asynchronous conversion modes, this core handles tens to hundreds of channels with conversion ratios from 1:24 to 24:1. Its memory-efficient architecture achieves –130 dB THD+N without requiring large lookup tables, making it a strong fit for systems requiring high fidelity and fast sync with minimal silicon overhead.
I2S/TDM Multichannel Audio Transceiver (I2S-TDM) — A full-duplex, multi-channel audio transceiver supporting I2S and TDM modes. Configurable as a master or a slave, designers can fine-tune sample rate, word width, frame format, and FIFO sizing, enabling tight integration into diverse audio architectures with lower gate count than many typical transceivers.
All these cores are supplied as Lint-clean Verilog RTL or FPGA netlists, are delivered with testbenches, simulation scripts, drivers, and documentation, and are backed by responsive, expert support.