LZ4SNP-C

LZ4/Snappy Data Compressor

LZ4SNP-C— a dual-format hardware compressor supporting both LZ4 and Snappy formats is well-suited for embedded systems, data storage controllers, networking devices, and edge/cloud accelerators where fast, flexible compression is critical. Its ability to produce standards-compliant output for either algorithm makes it ideal for platforms that must interface with third-party systems using different compression schemes. The core’s high-throughput, streaming design allows real-time compression of logs, telemetry, video metadata, or database records in ASIC or FPGA-based architectures. By combining performance with format versatility, LZ4SNP-C enables efficient bandwidth and storage reduction across applications in data centers, industrial automation, and mobile edge computing, without reliance on host processors or software libraries.

LZ4SNP-C is process-independent, and its silicon resource requirements and throughput depend on its configuration. The following table provides silicon resource utilization data for the core mapped on a 7nm ASIC technology with its clock set to 1,500MHz, which is not the maximum clock frequency the core can run at this technology. The core configurations listed on the table are indicative and represent a small subset of the possible configuration options.

The core’s throughput scales linearly with the number of block engines and is independent of the history size or compression algorithm. The LZ4SNP-C processes one input byte per clock cycle per block engine. In configurations with multiple block engines, achieving maximum throughput requires sufficiently sized buffers at the boundaries of each block engine. Please contact CAST to get characterization data for your target configuration and technology.

The LZ4SNP-C core can be mapped on any Altera FPGA, provided sufficient silicon resources are available. Its silicon resource requirements and throughput depend on its configuration. The following table provides sample resource utilization data for the core mapped on an Agilex™ 5 device (A5EC013AB23AE3V_E3) running at 270MHz. The core configurations listed on the table are indicative and represent a small subset of the possible configuration options.

The core’s throughput scales linearly with the number of block engines and is independent of the history size or compression algorithm. The LZ4SNP-C processes one input byte per clock cycle per block engine. In configurations with multiple block engines, achieving maximum throughput requires sufficiently sized buffers at the boundaries of each block engine. Please contact CAST to get characterization data for your target configuration and technology.

The LZ4SNP-C core can be mapped on any AMD FPGA, provided sufficient silicon resources are available. Its silicon resource requirements and throughput depend on its configuration. The following table provides sample resource utilization data for the core mapped on a Artix UtrlaScale+™ device (speed grade -1-e) running at 280MHz, which is not the fastest frequency for this device. The core configurations listed on the table are indicative and represent a small subset of the possible configuration options.

The core’s throughput scales linearly with the number of block engines and is independent of the history size or compression algorithm. The LZ4SNP-C processes one input byte per clock cycle per block engine. In configurations with multiple block engines, achieving maximum throughput requires sufficiently sized buffers at the boundaries of each block engine. Please contact CAST to get characterization data for your target configuration and technology.

Deliverables

The core is available in synthesizable HDL (SystemVerilog) or targeted FPGA netlist forms and includes everything required for successful implementation. Its deliverables include:

• Sophisticated SystemVerilog test environment
• Software Bit-Accurate model and test vector generator
• Simulation and synthesis scripts
• Comprehensive user documentation
• IP-XACT register descriptions