AES-GCM

AES-GCM Authenticated Encrypt/Decrypt Engine

An AES encryption operation transforms a 128-bit block into a block of the same size. The encryption key can be chosen among three different sizes: 128, 192 or 256 bits. The key is expanded during cryptographic operations.  

The AES algorithm consists of a series of steps repeated a number of times (rounds). The number of rounds depends on the size of the key and the data block. The intermediate cipher result is known as state. Initially, the incoming data and the key are added together in the AddRoundKey module. The result is stored in the State Storage area. 

The state information is then retrieved and the ByteSub, Shiftrow, MixColumn and AddRoundKey functions are performed on it in the specified order. At the end of each round, the new state is stored in the State Storage area. These operations are repeated according to the number of rounds.  

The final round is anomalous as the MixColumn step is skipped. The cipher is output after the final round. 

GCM mode 

A Galois Field (GF) multiplier/accumulator is utilized to generate an authentication tag while CTR (Counter) mode is used to encrypt. The counter value is initialized by an IV input from the user. 

During encryption or decryption, CTR mode is used to process the incoming data. An authentication tag up to 128 bits long is also produced by hashing with a GF multiply/accumulator additional data as well as the result of the CTR mode encryption or decryption. 

At the end of decryption, the user should verify that the authentication tag matches the original. If the former is different from the original, the authentication has failed. In this case no other information (i.e. no decrypted data or the value of the authentication tag) should be revealed except the failure itself. 

Key Expansion 

The AES algorithm requires an expanded key for encryption or decryption. The KEXP AES key expander core is available as an AES-GCM core option for the standard and fast versions. It is included for the higher throughput versions. During encryption, the key expander can produce the expanded key on the fly while the AES core is consuming it. For decryption, though, the key must be pre-expanded and stored in an appropriate memory before being used by the AES core. This is because the core uses the expanded key backwards during decryption. 

In some cases a key expander is not required. This might be the case when the key does not need to be changed (and so it can be stored in its expanded form) or when the key does not change very often (and thus it can be expanded more slowly in software). 

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in FPGA technologies. 
 

Support 

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. 

Deliverables 

The core is available in ASIC (RTL) or FPGA (netlist) formats, and includes everything required for successful implementation. The ASIC version includes 

•     HDL RTL source 
•     Sophisticated HDL Testbench (self-checking) 
•     C Model & test vector generator 
•     Simulation script, vectors & expected results 
•     Synthesis script 
•     User documentation 

The AES-GCM can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES-GCM Standard Core ASIC Implementation Results

Throughput for a 128-bit key size

AES-GCM Fast Core ASIC Implementation Results

Throughput for a 128-bit key size

AES-GCM High Throughput (-X) ASIC Implementation Results

AES-GCM Higher Throughput (-X2) ASIC Implementation Results

The AES-GCM can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Intel® results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES-GCM Standard Core Intel Implementation Results

Throughput for a 128-bit key size

AES-GCM Fast Core Intel Implementation Results

Throughput for a 128-bit key size

AES-GCM High Throughput (-X) Intel Implementation Results

AES-GCM Higher Throughput (-X2) Intel Implementation Results

The AES-GCM can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Xilinx results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES-GCM Standard Core Xilinx Implementation Results

Throughput for a 128-bit key size

AES-GCM Fast Core Xilinx Implementation Results

Throughput for a 128-bit key size

AES-GCM High Throughput (-X)  Xilinx Implementation Results

AES-GCM Higher Throughput (-X2)  Xilinx Implementation Results