xSPI-MC
xSPI, HyperBus™, and Xccela™ Serial Memory Controller

The xSPI-MC core is a versatile serial/SPI memory controller, which allows a system to easily detect and access the attached memory device or directly boot from it. The controller core supports most of the proprietary SPI protocols used by Flash and PSRAM device vendors and is compatible to JEDEC’s eXpanded SPI (xSPI), HyperBus™ and Xccela™ standards.

The core allows the system to interface with one or more serial memory devices in one of the following modes: a) in Slave mode by accessing its registers via an AHB slave interface, b) in DMA mode where the system programs the internal DMA engine, and then the core accordingly drives its AHB master interface, c) in Access In-Place (AIP) mode where the core allows the system to directly access the SPI memory address space via an AHB or AXI slave interface, d) in Boot-Image copy mode where after reset the core will autonomously copy an amount of data (boot-image) from the SPI memory to the AHB address space (e.g. on a shadow RAM, or DRAM) using its AHB master interface.

xSPI-MC can work with single, dual, quad, twin-quad, octal or 16x SPI memory devices. To enable use with memory devices from different vendors, the core offers two ways of configuring the device-specific parameters: a) via registers, where the system is responsible to identify the connected flash device and program the appropriate values to the core's registers, and b) by using the auto-configuration feature, where the core will autonomously identify the connected memory device and program itself accordingly. The auto-configuration functionality uses a user-provided memory that stores a list of automatically identifiable devices along with their features.

The xSPI-MC can be easily configured to match different application requirements. The instantiation of the DMA engine and the auto-configuration logic, the maximum number of memory devices that the core supports, and the reset values for all configuration registers, are some of the design parameters that can be controlled by means of simple Verilog defines.

The core can be implemented in any ASIC or FPGA technology, as it is delivered with a synthesizable soft-PHY, and does not use any process-specific modules. Sample timing constraints are provided with the core and optional technology mapping support is available.

The xSPI-MC is a highly configurable core and it is available in four versions as shown in the table below.

xSPI-MC Core Versions

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty consecutive days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

  • Verilog source or FPGA netlist

  • User Documentation

  • Testbench and sample synthesis and simulation scripts

The xSPI-MC can be mapped to any ASIC technology. Its size strongly depends on the configuration. Under its minimum configuration (XIP, no AIP, no DMA, no Auto-configuration) the core is about 12,000 gates. The SoC inter-faces (i.e. the AHB, AXI and APB) clocks can run at relatively high frequencies (e.g. 1GHz for 16nm). The speed of the SPI interface depends on the timing characteristics of the attached device, the target implementation technology, and the PHY implementation. Please contact CAST to get accurate characterization data for your target technology and configuration.

The xSPI-MC can be mapped to any Intel® FPGA device (provided sufficient silicon resources are available). Its size strongly depends on the configuration. Under its minimum configuration (XIP, no AIP, no DMA, no Auto-configuration) the core is about 1,000 ALMs. The SoC interfaces (i.e. the AHB, AXI and APB) clocks can run at relatively high frequencies (e.g. 150MHz on Arria® 10 GX speed grade 5). The speed of the SPI interface depends on the timing characteristics of the attached device, and the target FPGA device. Please contact CAST to get accurate characterization data for your target technology and configuration.

The xSPI-MC can be mapped to any Xilinx® FPGA device (provided sufficient silicon resources are available). Its size strongly depends on the configuration. Under its minimum configuration (XIP, no AIP, no DMA, no Auto-configuration) the core is about 1,200 LUTs. The SoC interfaces (i.e. the AHB, AXI and APB) clocks can run at relatively high frequencies (e.g. 250MHz on Kintex®-7). The speed of the SPI interface depends on the timing characteristics of the attached device, and the target FPGA device. Please contact CAST to get accurate characterization data for your target technology and configuration.

Related Content

Weight in Family
10.00

Features List

SPI Memory Controller

  • Supports xSPI (JEDEC’s JESD251), HyperBus™, Xccela™ and most proprietary SPI memory interfaces
  • Works with Serial NOR flash, NAND-Flash, PSRAM and HyperRAM™ devices 
     

Flexible Access Modes

  • AIP/XIP - Allows AHB bus masters to read (XIP) or optionally read and write (AIP) directly from the serial memory with zero software overhead 
  • DMA: Optional DMA engine can be programmed to transfer data from/to system to/from the serial memory
  • Boot-Image Copy: After reset the core uses its DMA engine to autonomously copy an amount of data from serial memory to the AHB address space
  • Slave Mode: System accesses core registers to transfer data to/from the serial memory 

Easy Integration & Operation

  • Run-time SPI protocol programmable parameters: 
    • Single, Dual, Quad, Twin-Quad, Octal and 16x SPI lanes
    • Single and Dual Transfer Rate (STR and DTR) SPI lanes
    • Bit-length and number of SPI lanes used for command, address, latency (dummy cycle), and data
    • Command encoding
  • Programming options: 
    • Automatically after reset - a list of automatically identifiable devices is provided to the core in an external memory 
    • At run time via configuration registers programming 
    • At synthesis time - Verilog defines for reset values of all configuration registers

Process-Independent Soft PHY

  • Synthesizable, soft PHY and sample timing constraints included

  • Optional technology mapping support is available

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