JPEG-DX-S
Baseline and Extended JPEG Decoder

The JPEG-DX-S IP core is an area-efficient, high-performance JPEG decoder conforming to the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard.   

It decompresses JPEG images, and also video payload for Motion-JPEG container formats. It supports 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. The decoder processes one color sample per clock cycle, enabling it to process multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG decoders available, it requires just 76,000 equivalent gates when mapped on an ASIC technology.  

Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed. 

SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.  

Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG decoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.  

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model. 

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products and is proven in both ASIC and FPGA technologies. 

Support 

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. 

Deliverables 

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms and includes everything required for successful implementation. The ASIC version includes: 

  • Verilog RTL source code 
  • Sophisticated self-checking Testbench  
  • Software (C++) Bit-Accurate Model  
  • Sample simulation and synthesis scripts 
  • Comprehensive user documentation 

The JPEG-DX-S core synthesizes to approximately 75K gates and requires 25k bits of memory. 

The JPEG-DX-S can be mapped to any Intel FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core.

  720p60 
4:2:0
1080p30 
4:2:2
1080p60 
4:2:0
Logic
Resources
MULTs/DSPs

Memory
Bits

Max10

 

 

 

10,400 LEs

10

33,344

CycloneV

 

 

 

4,200 ALMs

5

33,498

Arria10

 

 

 

4,200 ALMs

5

33,498

StratixV

 

 

 

4,200 ALMs

5

33,498


Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology. 

The JPEG-DX-S can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core. 

Family / Device Logic

Block
RAMs

DSP
Comp.

Fmax
(MHz)

ECP5U / LAE5U-12F

11.843 LUT4s
8,340 Slices

9 8 70


Note that the implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to discuss silicon resource utilization and performance for your target technology. 

The JPEG-DX-S can be mapped to any Xilinx Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core.

 

720p60
4:2:0

1080p30
4:2:2

1080p60
4:2:0

LUTs DSPs BRAMs

Artix-7 (-2)

      7,500 5 1 RAMB16

Kintex7 (-2)

      6,500 5 2 RAMB16

Kintex7-US (-1)

      5,350 5 3 RAMB16


Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology. 

Related Content

Weight in Family
11.00

Features List

Area-efficient, high-performance 8/12-bit JPEG decoder for ASICs and FPGAs 

Standards Support 

  • ISO/IEC 10918-1 Standard Baseline and Extended Decoder  (Sequential DCT modes) 
  • Single-frame JPEG images and Motion JPEG payloads 
  • Up to four color components 
  • 8- and 12-bit color samples 
  • All widely used color subsampling formats, and any image size up to 64k x 64k  
  • All scan configurations and all JPEG formats
  • All marker segments expect DNL 
  • Up to four Huffman Tables  
  • Up to four 8-bit or 16-bit Quantization tables  

Interfaces 

  • AXI Streaming I/O data interfaces 
  • APB Control/Status interface 
  • Optional AHB wrapper with DMA capabilities 

Performance and Size 

  • One decoded sample per clock cycle 
  • Small silicon footprint (~76k Gates) 

Ease of Integration 

  • Requires no programming or control from host  
  • Reports image format 
  • Detects and reports marker syntax errors 
  • Delivered with bit-accurate software model  
  • Optional Block-to-Raster Conversion with AXI or standard memory interface towards the lines buffer

Resources

See the JPEG entry at Wikipedia.

See the Motion JPEG entry at Wikipedia.

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