Silicon IP Cores
32-bit/33MHz Multi-Function PCI Target
The PCI-T32MF implements a target-only PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz (PCI clock).
The core offers one to eight independent PCI functions in a single chip, each implementing 64 to 256 bytes of PCI Configuration Space registers as required. Each function supports up to six Base Address Registers, with both I/O and Memory space decoding from 16 bytes up to 4GB.
The PCI- T32MF builds on more than 15 years of CAST PCI IP exper-tise and has been designed for straightforward reuse, with proven design practices that ensure easy integration and smooth technology mapping. The core is available in synthesizable RTL or as a targeted FPGA netlist, and is delivered with everything required for rapid and successful integration and implementation.
The core has been verified through extensive simulation and rigorous code coverage measurements.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes:
- HDL RTL source code
- Sophisticated HDL Testbench including vectors and ex-pected results
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script
- Comprehensive user documentation, including detailed specifications and a system integration guide
The PCI-T32MF can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.
The PCI-T32MF can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample implementation results assuming that only the PCI I/Os are routed off-chip, and the core is configured with slices using two functions, each of which having a single Base Address Register. Please contact CAST to get characterization data for your target configuration and technology.
- Fully compliant with the PCI Local Bus Specification, Revision 2.3.
- 33 MHz performance (PCI clock frequency)
- 32-bit datapath
- Full Target functionality, with support for these commands:
- Configuration Read, Configuration Write
- Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL), Memory Write and Invalidate (MWI)
- I/O Read, I/O Write
- Zero wait states burst mode
- Support all interrupt pins (INTA#, INTB#, INTC#, INTD#)
- Type 0 Configuration space
- Supports all Base Address Registers
- Supports backend initiated target retry, disconnect and abort
- Parity generation and parity error detection