Silicon IP Cores
The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using processors with AHB bus interfaces such as the BA22-DE, BA22-CE, ARM Cortex-M0/M0+/M1/M3/M4, and several RISC-V processors.
The AHB subsystem is available in two versions: Base and Extended. The Base version (AHB-SBS-BASE) integrates a 32-bit multilayer AHB fabric with an xSPI Flash Memory Controller, an SRAM controller and a set of APB peripherals. This version allows the host processor to boot directly from the flash, and execute code from the flash (eXecute In Place -XIP), or from an on-chip shadow SRAM. Furthermore, it provides access to the essential microcontroller peripherals, such as serial interfaces and timers.
The Extended version, the AHB-SBS-EXT, adds a multi-channel DMA, an SPI-to-AHB bridge, and an external memory controller, suitable for accessing off-chip parallel NOR-flash devices or SRAMs.
The AHB-SBS was designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. It is delivered in human-readable Verilog source code, along with comprehensive documentation for each module, example drivers, and. software exercising all the peripherals.
This subsystem can be mapped to any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.
Subsystem for microprocessors with 32-bit AMBA® 3.0 AHB-Lite or AHB Interfaces, such as:
- BA20, BA22-DE, BA22-CE
- ARM Cortex-M0/M1M3/M4
- Several RISC-V processors Integrated Modules
- AHB Multi-Layer Interconnect
- xSPI Flash Memory Controller
- Internal SRAM Controller
- APB Subsystem (APB-SBS):
- APB bridge.
- I2C Master/Slave,
- Octal SPI Master/Slave,
- 16550 UART,
- Real-Time Clock,
- Generic Timer,
- Watchdog Timer,
- Programmable Interrupt Controller
- Multichannel DMA
- SPI-to-AHB bridge
- External parallel flash or SRAM controller
- Number of extra AHB master and slave, and APB slave ports for user's modules
- AHB-slave port access per master
- Arbitration scheme per AHB slave-port
- Base address and size of address space per AHB and APB slave port.
- Integration with CAST or 3rd party IPs