SHA-3

SHA-3 Secure Hash Crypto Engine

The SHA-3 is a high-throughput, area-efficient hardware implementation of the SHA-3 cryptographic hashing functions, compliant to NIST's FIPS 180-4 and FIPS 202 standards. 
The core implements all the fixed-length and extendable hashing functions provisioned by these standards. The hashing function is synthesis-time configurable; a version supporting run-time hashing function selection can be made available upon request. 
The number of SHA-3 permutation rounds per clock cycle is configurable at synthesis time, allowing users to trade throughput for silicon resources. Under its minimum configuration of one permutation per cycle, the core processes 24 to 56 bits per cycle depending on the hashing function. This throughput can scale by a factor of 2x, 3x, or 4x by implementing 2, 3, or 4 permutations per cycle respectively, enabling throughputs in excess of 100Gbps in modern ASIC technologies. 
The core is designed for ease of use and integration and adheres to industry-best standards coding and verification practices. It requires no assistance from a host processor and uses standard AMBA® AXI4-Stream interfaces for input and output data. Technology mapping, timing closure, and scan insertion are trouble-free, as the core contains no multi-cycle or false paths, and uses only rising-edge-triggered D-type flip-flops, no tri-states, and a single-clock/reset domain. Its reliability and low risk have been proven through rigorous verification and FPGA validation.

Sample implementation results for a limited set of the SHA3 core configurations are provided in the following table.

Note that these sample implementation figures do not represent the highest speed or smallest area possible for the core.  

Sample implementation results a limited set of configurations implemented on an Intel® Arria10® (speed grade -2) device are provided in the following table.  

Note that these sample implementation figures do not represent the highest speed or smallest area possible for the core.

The SHA-3 can be mapped to any Microsemi device, provided sufficient silicon resources are available. Sample implementation results for a limited set of configurations implemented on an RTG4 (STD speed grade) device are provided in the following table. Please note that the figures on this table do not represent the highest clock frequency or smallest area possible for the core.

Sample implementation results for a limited set of configurations implemented on a Xilinx Kintex UltraScale+ (speed grade -1) device are provided in the following table. 

Note that these sample implementation figures do not represent the highest speed or smallest area possible for the core.