H.264 Video Over IP – HD Decoder Subsystem

This Video Over IP Subsystem integrates H.264 Decompression, Transport Stream and RTP/UDP/IP de-capsulation to enable the rapid development of complete video streaming products. Hardware reference designs and customization services complete the solution.

The subsystem uses the Low-Latency AVC/H.264 Baseline Profile Decoder Core and the RTP and UDPIP, hardware stacks available from CAST. Flexible interfaces allow easy integration of video, memory, and network controllers, and AXI4-Lite slave interfaces allow a host processor to access all control and status registers. An optional custom logic module allows standalone, processor-free operation and provides access to control and status registers via UDP packets. Video and stream data are transferred among the subsystem’s modules using AXI-Stream, making removing or adding modules straightforward.
The subsystem can decode Constraint Baseline Profile streams, encapsulated in RTP or plain UDP and features, sub-frame latency (no frame buffers are implemented). 

A turnkey reference design for Xilinx and Intel FPGA development boards (see Table below) is readily available. The reference design integrates the H264OIP-HDD -HDE Subsystem with Xilinx’s or Intel’s Ethernet MAC core. The reference design can be ported to other FPGA boards up on request.

FPGA Family and Platform Video-Out Stream In 3rd Party Cores Video Formats
Xilinx Kintex-7
HDMI 1G Ethernet Xilinx TEMAC and DDR3 controller LogiCores 720p30/60,
Intel Arria 10
HDMI 1G Ethernet Intel eMAC controller 720p30/60,
Intel Arria V
HDMI 1G Ethernet Intel eMAC controller 720p30/60,

CAST can integrate the H264OIP-HDD subsystem with your choice of video-out, memory, and network controllers. We can also modify it to support different CAST decompression cores. 

Related Content

Features List

  • Ultra-Low Latency H.264 Video Decompression
    • Constraint Baseline Profile
    • RTP and UDPIP Decapsulation
    • Sub-frame latency capable
  • Host interface via AXi4-Lite or processor-free UDP-controlled operation
  • AXI4-ST bus for Video & Stream data
  • Supports HD – 720p30/60 and Full-HD – 1080p30

Customization Options

  • Integration with Video-Outn Controllers (e.g., DVI, HDMI, MIPI-CSI, or SDI)
  • Integration with IP-based MAC controllers (e.g., Ethernet or 802.11 WiFi)

Reference FPGA Designs

  • Drive display via HDMI, on Xilinx or Intel boards
  • Can work with CAST’s H.264 Encoder Subsystem Reference Designs


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