Silicon IP Cores
The AC97-CTRL Audio Controller is a configurable IP block designed to simplify the integration of the AC'97 audio interface into ASIC and FPGA designs. Fully compliant with the Intel Audio Codec '97 (AC’97) Revision 2.3 specification, this controller facilitates reliable transmission and reception of stereo or multi-channel audio streams using the well-established AC-Link interface. With support for a single codec operating at a standard 48 kHz sample rate, the core is ideal for embedded applications that demand proven audio infrastructure with a compact silicon footprint and efficient data handling.
Control interface options include AXI-Lite, APB, and a generic microcontroller interface, while data transport is enabled through either AXI-Stream interfaces or a controller memory-mapped AXI interface driven by an integrated DMA. This enables both simple streaming applications and use cases requiring block transfers from system memory, such as audio playback from large buffers or real-time audio capture.
The AC97-CTRL core includes a complete set of power, reset, and synchronization management features. Designers can choose the bit clock source (controller or external codec), configure master clock division, and leverage cold/warm reset sequences with programmable timing. A tri-state management scheme ensures proper multi-device behavior on shared AC-Link signals, and interrupt signals provide real-time feedback for underrun and overrun conditions, reducing CPU load and improving reliability in time-sensitive applications.
The AC97-CTRL Controller Core is packaged with everything required for immediate deployment and verification, including lint-clean synthesizable Verilog, testbenches and simulation scripts for 100% coverage, synthesis scripts, Bare-metal driver and example firmware. Its modular architecture and rich configurability make it a strong fit for consumer audio systems, automotive infotainment units, industrial embedded platforms, and any application seeking a mature, standards-based audio interface with minimal integration risk.
The AC97-CTRL is a purely digital IP core that can be mapped to any ASIC technology. Its silicon resource requirements depend on its configuration. With a full AXI interface and DMA, it synthesizes to about 21K gates. The core interfaces can be clocked at frequencies exceeding 1GHz in most modern ASIC technologies.
Please contact CAST to get characterization data for your target configuration and technology.
The AC97-CTRL can be mapped to any Altera FPGA device (provided sufficient silicon resources are available). Its silicon resource requirements depend on its configuration. With a full AXI interface and DMA, it uses approximately 1.5k ALMs. The core interfaces can be clocked at frequencies exceeding 150 MHz in most Altera FPGA devices.
Please contact CAST to get characterization data for your target configuration and FPGA device.
The AC97-CTRL can be mapped to any AMD FPGA device (provided sufficient silicon resources are available). Its silicon resource requirements depend on its configuration. With a full AXI interface and DMA, it uses approximately 2.9k LUTs. The core interfaces can be clocked at frequencies of several hundred of MHz in most AMD FPGA devices.
Please contact CAST to get characterization data for your target configuration and FPGA device
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