MC-SDMA

Multi-Channel Streaming DMA Controller

The MC-SDMA IP core implements a highly configurable, bandwidth-efficient, and easy-to-use Direct Memory Access (DMA) controller that transfers data between the host system’s memory and multiple peripherals equipped with streaming interfaces.

The core interfaces with the host memory via a manager AMBA^® AXI4 (memory-mapped) port and provides access to its configuration and status registers (CSRs) via a subordinate AXI4-Lite or APB4 interface. Peripherals can be connected to the DMA controller via a configurable number of manager and subordinate AXI4-Stream interfaces, enabling both Host-to-Peripheral (H2P) and Peripheral-to-Host (P2H) data transfers.

Descriptors, one for each channel, are programmed with details of the data transfers through the CSR interface. Details include source (H2P) and destination (P2H) addresses, transfer size up to 2 GBytes, and control information. To further enhance workload handling, the MC-SDMA allows transfers to be split into smaller blocks. After each block’s transfer, the core arbitrates between competing DMA requests, enabling transfer interleaving and efficient bandwidth allocation. A number of memory locations can also be skipped after the transfer of each block of data, enabling the transfer of images, video frames, or graphics elements with a single descriptor. In the P2H direction, descriptors are updated with the actual transfer size—in case the peripheral asserts TLAST early—and with the value of the sideband TUSER bus. The H2P descriptors can enable the assertion of TLAST at the end of the transfer and control the value of the TUSER bus.

The MC-SDMA is highly configurable both at synthesis and runtime, allowing it to be tailored to specific application requirements. Synthesis parameters include the number of P2H and H2P channels, instantiation and sizing of FIFOs, and address and data-bus widths. Runtime programmability includes channel priority order, maximum transfer burst length, and interrupt triggers.

The MC-SDMA core is rigorously verified, LINT-clean, and scan-ready. It is available in synthesizable Verilog and FPGA netlist forms and includes everything required for successful implementation, including a UVM testbench, simulation, and synthesis scripts, and comprehensive user documentation.