Silicon IP Cores
AHB Cache Controller
The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave processor interface and a 32-bit master interface to the memory subsystem. The processor and memory interfaces are natively AHB5 and can easily be reduced to AHB-lite.
The cache controller core supports a four-way associative cache memory and implements a Least Recently Used (LRU) replacement policy. The number of cache lines and the cache line width are configurable at synthesis time. The core only caches read accesses and invalidates the cached data if a write-access to a cached memory location occurs.
Mapping the cache controller to any technology is straightforward, as the core does not require any special type of SRAM modules, only using standard, single-ported SRAMs. Furthermore, the design is scan-ready as it uses only rising-edge triggered flip-flops and contains no internal tri-states. Integration of the core is trouble-free, as the core uses standard 32-bit AHB interfaces and supports clock gating.
The CACHE-CTRL core has been robustly verified and is silicon-proven.
The CACHE-CTRL can be used to add single or multilevel cache memory to cache-less deeply embedded processors, DSPs, or ASIPs. This can decrease the read access time and bandwidth to a relatively slow or energy-consuming memory resource like flash, EEPROM, or DRAM devices. For example, it allows embedded processors like the BA2x, or the RISC-V BA51, or ARM’s Cortex-M to run code directly from an off-chip NOR-flash (XIP) while minimizing the typical performance and/or power penalties of off-chip access.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core interfaces and the cache’s parameters (e.g., associativity, or replacement policy) can be customized. Please contact CAST to discuss your project requirements.
- Verilog RTL source code or tar-geted FPGA netlist
- Verification environment using System Verilog Assertions and Bus Functional Models
- Sample synthesis and simulation scripts
- User Documentation
CACHE-CTRL reference designs have been evaluated in a variety of technologies. When configured with eight words per line and 256 lines per set (1024 lines in total) the core synthesizes to about 10,000 equivalent NAND2 gates. It can run over 1GHz when mapped in a typical 28nm technology. Please contact CAST to get resource utilization and performance information for your preferred core configuration and ASIC technology.
The CACHE-CTRL core can be mapped in any Intel® FPGA device. When configured with eight words per line and 256 lines per set (or 1024 lines in total) it synthesizes to about 3,300 ALMs. The core can run over 200 MHz on Arria® 10 devices. Please contact CAST to get resource utilization and performance information for your preferred core configuration and FPGA device(s).
The CACHE-CTRL core can be mapped to any Xilinx® FPGA device. When configured with eight words per line and 256 lines per set (or 1024 lines in total) it synthesizes to about 2,000 LUTs and can run with over 100MHz in most 7-Series devices. Please contact CAST to get resource utilization and performance information for your preferred core configuration and FPGA devices.
Adds single or multilevel cache memory to originally cache-less deeply embedded processors, DSPs, or ASIPs.
Improves access time and reduces bandwidth to DRAM, Flash or EEPROM memories; enables XIP without typical power or performance penalties.
- Four-way set-associative cache
- Least Recently Used (LRU) replacement policy
- Synthesis-time configurable:
- number of cache lines
- number of words per line
- 32-bit words
- Invalidates cache contents if a write access occurs
Easy Integration & Implementation
- AHB5 or AHB-lite interfaces
- 32-bit slave port towards the processor
- 32-bit master port towards the memory system
- Uses four single-ported SRAMs: no special type of RAM is required
- Scan-ready design
- Supports clock gating