Silicon IP Cores
UART with Synchronous CPU Interface
The H16450S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16450 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices.
Developed for easy reuse in ASIC and FPGA applications, the H16450S is available optimized for several technologies with competitive utilization and performance characteristics.
The H16450 includes the following six major blocks. All the core’s inputs and outputs are fully synchronous to the rising edge of the CLK input.
Handles communication with the processor (or parallel) side of the system. Manages all writing and reading of internal registers.
Holds all of the device’s internal registers. Some information comes from the other blocks, however register information is gathered in the UART Registers block and made available to all blocks.
Handles the receiving of the incoming serial word. It is programmable to recognize data widths such as 5, 6, 7 or 8 bits, various parity settings, and different stop bits of 1, 1½ and 2 bits. It checks for errors in the input data stream such as overrun errors, frame errors, parity errors and break errors. If the incoming word has no problems it is placed in the Receiver Holding register.
Sends an interrupt signal back to the processor depending on the state of the received and transmitted data. There are various levels of interrupt which can be read from the Interrupt Identification register, which gives the level of interrupt. Interrupts are sent in the condition of empty transmission or receiving buffers, an error in the receiving of a character, or other conditions requiring the attention of the processor.
Baud Rate Generator
This block takes the input clock, CLK, and divides it by a programmed value (from 1 to 216 – 1). This divided clock is then divided by 16 to create the transmission clock called the Baudout clock.
The Transmit block handles the transmission of data written to the Transmission Holding register. It adds required start, parity and stop bits to the data being transmitted so that the receiving device can do the proper error handling and receiving.
The H16450S core is modeled after the Texas Instruments 16450, with the following differences:
- No provision is made for a crystal. The CLK input is designed to accept a standard digital input.
- The RCLK input in the Asynchronous version is replaced by CLK.
- The bi-directional Data Bus has been split into an input and an output component. In order to use the core with a bi-directional Data Bus, the DDIS signal can be used as the controlling signal for the tri-state drivers.
- RDN, WRN CS1 and CS2N have been eliminated. A single signal takes their place. These are RD, WR and CS.
- The ADSN signal has been removed. The H16450S functions as if the ADSN signal is held low. The included wrapper can be used to add the ADSN functionality latching the address and data buses.
- The main clock input CLK must be active from power-up.
- The Baudrate Generator is reset to the 0001h value upon activation of the MR signal. Programming the BRG to 0000h is an illegal value. The minimum value for the BRG is 0001h. The Output Data Bus always shows the value of the last register read.
- The Output Data Bus always shows the value of the last register read.
The core has been verified through extensive synthesis, place and route, and simulation runs. It has been embedded in several shipping customer products, and is proven in both ASIC and FPGA technologies.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts and comprehensive user documentation.
H16450S reference designs have been evaluated in a variety of technologies. The following are sample results:
|TSMC 40 nm
|TSMC 28 nm
|TSMC 16 nm
Please contact CAST to get characterization data for your target configuration and technology.
The H16450S can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data with all core I/Os routed off-chip and slices optimized for area. Please contact CAST to get characterization data for your target configuration and technology.
The H16450S can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data optimized for speed. Please contact CAST to get characterization data for your target configuration and technology.
- Capable of running all existing 16450 software
- Fully Synchronous design. All inputs and outputs are based on the rising edge of clock
- Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
- Independently controlled transmit, receive, line status and data set interrupts
- Programmable baud generator divides any input clock by 1 to (2**16 - 1) and generates the 16 x clock
- Modem control functions (CTSn, RTSn, DSRn, DTRn, RIn, and DCDn)
- Fully programmable serial interface characteristics:
- 5, 6, 7, or 8 bit characters
- Even, odd, or no-parity bit generation and detection
- 1, 1½, or 2 stop bit generation
- Baud generation
- False start bit detection
- Complete status register
- Internal diagnostic capabilities: loopback controls for communications link fault isolation
- Full prioritized interrupt system controls