CAN-CTRL
CAN 2.0, CAN FD, and CAN XL Bus Controller

Implements a CAN bus controller that performs serial communication according to the CAN 2.0, CAN FD, and CAN XL specifications. It supports the original Bosch protocol and ISO specifications as defined in ISO 11898—including time-triggered operation (TTCAN) as specified in ISO 19898-4—and is also optimized to support the popular AUTOSAR and SAE J1939 specifications. 

The CAN protocol uses a multi-master bus configuration for the transfer of frames between nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up economic and reliable links between various components. It appears as a memory-mapped I/O device to the host processor, which accesses the CAN core to control the transmission or reception of frames.

The CAN-CTRL core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic 32-bit or 8-bit processor interface or optionally a 32-bit AMBA APB, AHB-Lite, Wishbone, or Avalon-MM interface. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application.

The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). The PTB can store one message, while the number of included buffer slots for the STB is synthesis-time configurable. The transmit buffer can operate in FIFO or priority mode. 

The core implements functionality similar to the Philips SJA1000 working with its PeliCAN mode extensions, providing error analysis, diagnosis, system maintenance, and optimization features.  

The CAN-CTRL is extensively verified, proven in several plugfests and a large number of production designs.

The CAN bus controller comes in three variants: 2.0, FD, and XL. The 2.0 variant supports only the CAN 2.0 specification, the FD variant adds support for CAN FD, and the XL variant supports the CAN 2.0, CAN FD, and CAN XL standards.

Each of the three core variants is available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO-26262 ASIL-D Ready. 

Verification

The core has been rigorously verified and has been production-proven multiple times.
It has been verified through extensive synthesis, place and route, simulation runs, Verification IP, and PlugFests. It has been embedded in several shipping customer products and is proven in both ASIC and FPGA technologies.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core includes everything required for successful implementation:

  • VHDL or Verilog RTL source code
  • Post-synthesis netlist 
  • Testbenches
    • Behavioral tests
    • Post-synthesis verification
  • Simulation scripts
  • Synthesis scripts
  • Linux driver
  • Documentation, and RUVM register descriptions
  • The optional safety-enhanced package includes the Safety Manual (SAM), a Failure Modes, Effects and Diagnostics Analysis (FMEDA) and the ASIL-D Ready certificate, issued by SGS-TÜV Saar GmbH.

The CAN-CTRL can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include priority mode, TTCAN and CiA603 timestamping). 

Configuration Technology Cell Area
(eq. Gates)
Memory
Bits
CAN 2.0 TSMC 28nm HPC 9,000 2,688
CAN FD TSMC 28nm HPC 11,000 6,272
CAN XL TSMC 28nm HPC 15,000 133,248
CAN 2.0 – Safe TSMC 28nm HPC 30,000 3,864
CAN FD – Safe TSMC 28nm HPC 35,000 9,212
CAN XL – Safe TSMC 28nm HPZ 45,000 216,528

Please contact CAST to get characterization data for your target configuration and technology.

The CAN-CTRL can be mapped to any Intel FPGA device (provided sufficient silicon resources are available). The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include priority mode, TTCAN and CiA603 timestamping).

Family Device CAN 2.0 CAN-FD
Logic Memory Logic Memory
Max 10
10M50
2,343 LEs
0 MULTs
1,088 bits
3 RAM Blocks
2,806 LEs
0 MULTs
4,224 bits
3 RAM Blocks
Cyclone V
5CEFA7
1,094 ALMs
1 DSP
1,325 ALMs
1 DSP
Cyclone 10 LP
10CL120
2,331 LEs
0 MULTs
2,808 LEs
0 MULTs
Cyclone 10 GX
10AX115
1,072 ALMs
1 DSP
1,317 ALMs
1 DSP
Arria V GX
5AGXBB3
1,092 ALMs
1 DSP
1,217 ALMs
1 DSP
Arria 10 GX
10AX115
1,117 ALMs
1 DSP
1,333 ALMs
1 DSP

Note: Host and CAN clock constrained to 80MHz

When CAN XL support is added, the CAN-CTRL core occupies approximately 1,750 ALMs and requires 133k of memory bits.
Please contact CAST to get characterization data for your target configuration and technology.

The CAN-CTRL can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements.. The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include TTCAN, or CAN-XL).

Family & Device CAN-FD Support Logic Block RAMs Host Clock (MHz) CAN Clock (MHz)
ICE
40U/P5k
Yes 3,883 LCs
544 PLBs
6 42 25
ICE
40U/P5k
No 2,932 LCs
452 PLBs
6 45 25
MachXO2
7000HC
Yes 1,530 Slices
3,025 LUT4s
4 59 23
MachXO2
7000HC
No 1,248 Slices
2,466 LUT4s
0 62 29
ECP5
LFE5U-85F
Yes 1,810 Slices
2,752 LUTs
2 80 80
ECP5
LFE5U-85F
No 1,444 Slices
2,135 LUTs
2 80 80

CAN-CTRL reference designs have been evaluated in a variety of technologies. The following are sample results optimized for area with three receive buffers, three transmit buffers, and three acceptance filters (standard version, no TTCAN).

Family Variant Logic
Resources
Memory
Resources
Freq.
(MHz)
Igloo2
M2GL150-STD
CAN 2.0 2,774 4LUT 2 RAM1K18 60
Igloo2
M2GL150-STD
CAN FD 3,330 4LUT 2 RAM1K18 60
PolarFire
MPF500T-STD
CAN 2.0 2,759 4LUT 2 LSRAM 100
PolarFire
MPF500T-STD
CAN FD 3,375 4LUT 2 LSRAM 100
RTG4
RT4G150-STD
CAN 2.0 2,711 4LUT 2 RAM1K18 60
RTG4
RT4G150-STD
CAN FD 3,416 4LUT 2 RAM1K18 60
SmartFusion2
M2S150-STD
CAN 2.0 2,774 4LUT 2 RAM1K18 60
SmartFusion2
M2S150-STD
CAN FD 3,330 4LUT 2 RAM1K18 60

The CAN-CTRL can be mapped to any Xilinx FPGA device (provided sufficient silicon resources are available).  The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include priority mode, TTCAN, and CiA603 timestamping).

Configuration Device Family
Artix-7 Virtex 7 Kintex US Kintex US+
CAN 2.0 1,847 LUTs
1 BRAM Tile
1,855 LUTs
1 BRAM Tile
1,822 LUTs
1 BRAM Tile
1,823 LUTs
1 BRAM Tile
CAN 2.0 – Safe 6,993 LUTs
1.5 BRAM Tile
6,979 LUTs
1.5 BRAM Tile
6,924 LUTs
1.5 BRAM Tile
6,925 LUTs
1.5 BRAM Tile
CAN FD 2,270 LUTs
1 BRAM Tile
2,266 LUTs
1 BRAM Tile
2,250 LUTs
1 BRAM Tile
2,244 LUTs
1 BRAM Tile
CAN FD – Safe 8,353 LUTs
1.5 BRAM Tile
8,291 LUTs
1.5 BRAM Tile
8,347 LUTs
1.5 BRAM Tile
8,327 LUTs
1.5 BRAM Tile
CAN XL 3,423 LUTs
8 BRAM Tile
3,417 LUTs
8 BRAM Tile
3,465 LUTs
8 BRAM Tile
3,467 LUTs
8 BRAM Tile
CAN XL – Safe 12,071 LUTs
13 BRAM Tile
12,012 LUTs
13 BRAM Tile
11,767 LUTs
13 BRAM Tile
11,747 LUTs
13 BRAM Tile


Please contact CAST to get characterization data for your target configuration and technology.

Related Content

Weight in Family
18.00
Image
CAST CAN 2.0, CAN FD & CAN XL Controller IP Core

Features List

CAN Specifications Support

  • CAN 2.0 & CAN FD (ISO 11898-1.2015, plus earlier ISO and Bosch specifications) 
  • CAN XL (CiA 610-1 specification)
  • TTCAN (ISO 11898-4 level 1) 
  • Optimized for AUTOSAR and SAE J1939

Enhanced Functionality

  • Error Analysis features enabling diagnostics, system maintenance, and system optimization:
    • Last error type
    • Arbitration lost position
    • Error Warning Limit
  • Listen-Only Mode enables CAN bus traffic analysis and automatic bit-rate detection
  • Loop back mode for self-testing
  • Time-stamping support, compliant to CiA's 603 specification

Flexible Message Buffering and Filtering

  • Configurable number of:
    • Receive buffers
    • Lower-priority transmit buffers
    • Independently programmable acceptance filters, 1 to 16
  • One high-priority transmit buffer
  • FIFO or priority mode for transmit buffers

Easy to Use and Integrate

  • Programmable data rate up to 1 Mbit/s with CAN 2.0 and several Mbit/s with CAN FD or CAN XL option
  • Programmable baud rate prescaler: 1 up to 1/256
  • Single Shot Transmission Mode for lower software overhead and fast reloading of transmit buffer
  • Programmable interrupt sources
  • Generic 32-bit or 8-bit host-controller interface and optional 32-bit AMBA-APB, 32-bit AHB-Lite, 32-bit Wishbone, or 32-bit Avalon-MM
  • A single host can control multiple CAN bus nodes via an optional Multi-CAN wrapper

Safety Enhanced Version (optional)

  • ISO-26262 ASIL-D Ready
    • Implements ECC for SRAM and spatial redundancy for inner logic protection

Zero Risk

  • Compatible with any CAN2.0 transceiver (PHY) that supports ISO-11898, and various CAN-FD PHYs from NXP, MicroChip, OnSemi, Infineon, etc.
  • Multiple times production-proven

Efficient and Portable Design

  • Available in RTL, and portable to ASIC and FPGA technologies

Verification IP

Available for this core: CAN-VIP

Resources

Resources

Articles

 

Let's talk about your project and our IP solutions

Request Info