An introduction to Time-Sensitive networking (TSN) and how it makes Ethernet a suitable backbone for complex automotive and industrial systems.
Jun 22, 2019
Silicon IP Cores
CSENT-RX
SENT/SAE J2716 Receiver
The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous sensors. It can be used for receiving data from one or multiple sensors using a single SENT line. The CSENT-RX provides access to its control, status, and data registers via a 32-bit APB, or AXI4-Lite bus interface, and the reset values for all its control registers are defined at synthesis time. The core provides a glitch filter on the serial data input and has data mapping functionality on received data to offload the connected host from data formatting. An external metadata port allows the host system to add customized metadata (e.g. timestamps) into the received data stream. The received data are accessible via the register interface. The core is also capable of generating trigger pulses requesting synchronous sensors to send data. The generation of trigger pulses is controlled via a dedicated input pin, or via a control register. A set of handshaking signals facilitates the integration with an external DMA controller. An extended set of interrupt sources includes detection of calibration variation, timeout errors, frequency drift error, FIFO-related triggers, frames’ validity and numerous frame’s errors. The CSENT-RX core is designed with industry best practice, has been rigorously verified and is production proven.
The core can be mapped to any ASIC technology and any FPGA device. The following are sample implementation results, which do not represent the highest speed or smallest area possible for the core and exclude the FIFOs.
CSENT-RX
| Target Technology | Core Configuration | Logic Resources | Freq |
| TSMC 180g |
No data mapping
No Metadata
CRC4 only
No synchronous Trigger Pulse Frame
No Timeout Functionality
|
8,397 Gates
|
400 MHz
|
| TSMC 40g |
7,600 Gates
|
400 MHz
|
|
| TSMC 28hpc | 6,238 Gates | 400 MHZ | |
| TSMC 16 | 6,904 Gates | 400 MHz | |
| TSMC 180g |
Data mapping and Metadata |
13,345 Gates |
400 MHz |
| TSMC 40g | 11,840 Gates | 400 MHz | |
| TSMC 28hpc | 9,775 Gates | 400 MHz | |
| TSMC 16 | 10,792 Gates | 400 MHz |
The CSENT-RX core can be mapped to any Altera FPGA device provided sufficient resources are available. The following are sample implementation results, which do not represent the highest speed or smallest area possible for the core and exclude the data FIFOs.
| Target Technology | Core Configuration | Logic Resources | Freq |
|---|---|---|---|
| Agilex 5 A5EA013BB23BE5S |
No data mapping No metadata CRC4 only No synchronous Trigger Pulse Frame No Timeout functionality |
621 ALMs | 275 MHz |
| Arria 5GX 5AGXBB3D4F35C5 |
696 ALMs | 175 MHz | |
| Cyclone 10GX 10CX220YF672I5G |
620 ALMs | 275 MHz | |
| Agilex 5 A5EA013BB23BE5S |
Data mapping and Metadata CRC4, CRC6 and CRC8 Synchronous Trigger Pulse Frame Timeout functionality |
933 ALMs | 275 MHz |
| Arria 5GX 5AGXBB3D4F35C5 |
901 ALMs | 150 MHz | |
| Cyclone 10GX 10CX220YF672I5G |
906 ALMs | 275 MHz |
The CSENT-RX core can be mapped to any AMD FPGA device provided sufficient resources are available. The following are sam-ple implementation results, which do not represent the highest speed or smallest area possible for the core and exclude the data FIFOs.
| Target Technology | Core Configuration | Logic Resources | Freq |
|---|---|---|---|
| Artix Ultrascale+ xaau15p-1-i |
No data mapping No metadata CRC4 only No synchronous Trigger Pulse Frame No Timeout functionality |
793 LUT | 550 MHz |
| Kintex Ultrascale xcku085-1-c |
757 LUTs | 350 MHz | |
| Artix UltraScale+ xaau15p-1-i |
Data mapping and Metadata CRC4, CRC6 and CRC8 Synchronous Trigger Pulse Frame Timeout functionality |
1,443 LUTs | 450 MHz |
| Kintex UltraScale xcku085-1-c |
1,432 LUTs | 300 MHz |
The CSENT-RX core can be mapped to any Microchip FPGA device provided sufficient resources are available. The following are sample implementation results, which do not represent the highest speed or smallest area possible for the core and exclude the data FIFOs.
| Target Technology | Core Configuration | Logic Resources | Freq |
|---|---|---|---|
| Igloo2 M2GL150-STD |
No data mapping No metadata CRC4 only No synchronous Trigger Pulse Frame No Timeout functionality |
1,086 4LUT | 170 MHz |
| PolarFire MPF300T-STD |
1,074 4LUT | 270 MHz | |
| RTG4 RT4G150-STD |
1,049 4LUT | 120 MHz | |
| Igloo2 M2GL150-STD |
Data mapping and Metadata CRC4, CRC 6 and CRC8 Synchronous Trigger Pulse Frame Timeout functionality |
2,421 4LUT | 150 MHz |
| PolarFire MPF300T-STD |
2,285 4LUT | 240 MHz | |
| RTG4 RT4G150-STD |
2,179 4LUT | 110 MHz |
Features List
SENT/SAE J2716 Receiver
- Fast and Slow Channel
- 4, 6 or 8-bit CRC checking
- Programmable Glitch filter
- All types of SENT Frames
- Programmable data length (1 to 8 nibbles) for Fast Channel Frames
- Short (8-bit data) and Enhanced (12- or 16-bit data) Message Formats for Slow Channel
- Fast Channel data mapping to reduce host/CPU overhead
- Customized metadata support
- Supports inverted SENT protocol
Trigger Pulse for Synchronous Sensors
- Allows up to four sensors (transmitters) to use the same physical SENT connection
- Programmable trigger pulse length
- Activated via software or hardware
Ease of Integration
- 32-bit APB or AXI4-Lite interface, and comprehensive set of interrupts
- Programmable reference counter to validate calibration pulses
- Optional Receive FIFO of configurable size for Fast Channel data
- Run-time programmable configuration registers
- Synthesis-time defined reset values for all registers, enables data reception without control from host processor
- LINT-clean, single-clock domain, scan-ready design
Deliverables
- RTL source code or targeted FPGA netlist
- SystemVerilog Testbench
- Sample synthesis and simulation scripts
- Documentation
- IP XACT register definitions