Silicon IP Cores
40G UDP/IP Hardware Protocol Stack
A UDP/IP hardware stack for high-speed communication over a LAN or a point-to-point connection, with speeds up to 40Gbps even in processor-less SoC designs.
GZIP/ZLIB/Deflate lossless compression and decompression cores, verification IP, and reference designs, for significantly reducing bandwidth and storage requirements ...
From simple SENT and LIN to advanced TSN Ethernet, and featuring the most robust CAN FD Bus Controller available anywhere.
TSN Ethernet Switched Endpoint Controller
The TSN-SE implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards ...
SoC Security Platform
A flexible, efficient hardware root of trust platform for SoC designs that works with any microprocessor architecture. Provides secure boot and optionally supports ...
Universal Serial Flash Controller
A controller for nearly any standard flash device, enabling detection and access or booting. Supports the popular SPI protocols and is compatible with JeDEc’s ...
Tiny Baseline JPEG Encoder
On e of the smallest JPEG Encoders available, with very low latency and support for the Baseline Sequential DCT and the Extended Sequential DCT ISO/IEC 10918-1 ...
Super-Fast 8051 Microcontroller with Configurable Features & Peripherals
One of the fastest-available, low-energy, 8-bit MCS®51 microcontrollers, with a configurable range of features and integrated peripherals.
PipelineZero 32-bit Embedded Processor
A royalty-free, ultra-low-power 32-bit embedded processor with very high efficiency—up to 3.48 CoreMarks/MHz—and a tiny silicon footprint. Standard and optional ...
ASIC and FPGA IP core is ready to reduce development time and risk for automotive system designers using Time Sensitive Networking (TSN) Ethernet.
Enables easy implementation of small, low-power, low-latency TSN Ethernet nodes for daisy-chained or ring networks.
Low-latency Video Decoding IP Subsystem Meets Megh's Requirements for Video Analytics System Using AI/Deep Learning to Prevent Retail Inventory Loss
Jan 8, 2020
Commercially proven AES encryption and decryption engines now certified to meet standard for function and interoperability.
IP core provides easy integration of up to seven CAN buses with an Ethernet network in automotive and industrial systems; will be shown at TSN/A Conference.
Reduce bandwidth and storage requirements with standard GZIP/ZLIB/Deflate compression at over 90Gbps on Xilinx Alveo Data Center Accelerator Cards.