32-bit Application Processor

The royalty-free BA25 is a 32-bit processor for demanding systems running applications on general-purpose operating systems such as Linux and Android. The high-performance BA25 processor runs at high clock frequencies yet has a smaller silicon footprint than most competing application processors (e.g., over 1100MHz and from 145K µm2 in TSMC 28nm HPM, including the FPU, and excluding SRAMs).

The BA25 is binary-compatible with other members of the silicon-proven BA2x processor family. Its BA2 instruction set is relatively simple and extremely compact, offering system area and energy savings benefits. Programing is facilitated with the included C/C++ tool chain, Beyond Studio™ Eclipse-based IDE, architectural simulator, and ported C libraries, RTOSs, and OSs.

The royalty-free, high-performance BA25 processor core is suitable as the main system processor in a multitasking environment and is a competitive choice for designs running full operating systems such as Linux or Android. 

The seven-stage pipelined architecture runs at high frequencies and further enhances performance by supporting out-of-order execution and branch prediction. An optional IEEE 754 compliant floating-point unit accelerates floating-point computations.

The BA25 processor uses two-level data and instruction caches—with L0 running at the CPU’s clock frequency and L1 running at half that—and a two-level memory management unit. The size and associativity of the caches and MMU are configurable at synthesis time. The system interface uses two AMBA® AXI4™ buses, one for data and one for instructions, both of configurable data width. Two tightly-coupled quick memory (QMEM) buses allow fast access for time-critical code and data, and can be used for inter-core communication in a multi-core architecture.

The energy efficiency BA25 enables power management with clock gating and power shut-off of unused units, and through software and hardware control over the clock frequency of the CPU and buses. Wake up from sleep mode is triggered by an interrupt issued by the embedded tick timer or by an external source.

The BA2 instruction set provides extreme code density without compromises on performance, ease of use, or scalability. It features: 

  • A linear, 32-bit address space 
  • Variable length instructions: 16, 24, 32, or 48 bits 
  • Simple memory addressing modes 
  • 12 to 32 general purpose registers  
  • Efficient flow-control, arithmetic, and load/store instructions 
  • Floating point and DSP extensions  

The core is delivered with BeyondStudio™, a complete Integrated Development Environment (IDE) for Windows and Linux under Eclipse. BeyondStudio includes a highly featured source code editor, supports graphical source-level debugging and GUI based configuration, and can be extended with a collection of available or custom plug ins.

The IDE integrates an Instruction level simulator and a GNU cross-compiling toochain. The GNU Compiler Collection (GCC), includes front ends for C, C++, Objective-C, Fortran, Java, and Ada; libraries for these languages (e.g. libstdc++, libgcj, etc) are provided. The toolchain also includes the GNU Binutils collection of binary tools, and the GNU Project Debugger (GDB).

Extensive support of libraries enables easy application development for Linux and Android. Finally, hardware targets can be interfaced with the cost effective Beyond Debug Key, which in addition to standard JTAG (IEEE 1149.1 and IEEE 1149.7) also supports proprietary One Wire Debug and Two Wire Debug protocols.

Support and Services 

The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

IP Integration Services are also available to help minimize time to market for BA25-based systems. The processor core can be delivered pre-integrated with typical peripherals such us UARTs, timers and serial communication cores, or with memory controllers and interconnect IP cores. Contact CAST Sales for details.


The core is available for ASICs in synthesizable Verilog source code or for FPGAs in optimized netlists. It includes everything required for successful implementation: extensive documentation, a testbench, sample synthesis and simulation scripts, and the BeyondStudio™ Eclipse-based software development IDE for Windows and Linux.

Reference designs on FPGA boards are also available; contact CAST Sales for information.

Related Content

Features List

High Performance 32-bit CPU 

  • Seven-Stage Pipeline 
  • Out-of-Order Completion 
  • Sophisticated Branch Prediction 
  • Optional Floating Point Unit 
  • 2.51 Coremarks/MHz 
  • 1100+ MHz on TSMC 28nm HPM 

Efficient Power Management  

  • Dynamic clock gating and power shut off of unused units 
  • Software- and hardware-controlled clock frequency  
  • Wake up on tick timer or external interrupt 

Fast & Flexible Memory Access 

  • Separate Instruction and Data Caches and MMU  
    • AXI4 data & instruction buses (32-, 64- or 128-bit) with 4 GBytes direct addressable space on each bus 
  • Tightly coupled Quick Memory (QMEM) interface for fast and deterministic access to code and/or data 

Two-Level Cache and MMU 

  • L0 cache running at core frequency and L1 cache running at half the core frequency 
  • 1–16 Kbytes L0 caches, up to four-way set associative 
  • 32–512 Kbytes L1 caches, up to four-way set associative 
  • L0 MMU with up to 32 four-way associative entries 
  • L1 MMU with up to 2048 four-way associative entries 

Optional Integrated Peripherals 

  • Vectored Interrupt Controller  
  • Microcontroller peripherals such as GPIO, UART, Real-Time Clock, Timers, I2C, and SPI 
  • Memory controllers, interconnect IP, and more 

Easy Software Development  

  • Non-intrusive JTAG debug/trace for both CPU and system 
  • Complex chained watchpoint and breakpoint conditions 
  • BeyondStudio™ complete IDE for Windows or Linux under Eclipse 
  • Ported libraries and operating systems 

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