Silicon IP Cores
Time Sensitive Networking – An Introduction to TSN
by Dr. Andreas Weder,
Fraunhofer Institute for Photonic Microsystems (IPMS)
Ethernet has been equally established as a dependable wired solution in both computer and automation networks. The open standard allows terminals to be quickly and simply connected as well as easily scaled to exchange data with relatively inexpensive hardware. Ethernet was, however, not originally designed to meet the requirements posed by automation technology, particularly in regards to guaranteed and real-time communication. Therefore, various bus systems in automation have evolved using Ethernet on a physical level while implementing proprietary real-time protocols on top. These systems often lead to the exclusive use of the network infrastructure as well as vendor dependencies. Such networks handling time-critical data traffic are today separated from networks directing less-critical data traffic in order to eliminate reciprocal negative interference. In the future, Industry 4.0 applications will require increasingly more consistent Ethernet networks. Such networks can only be produced at great cost with the traditional structure.
Time-Sensitive networking (TSN) provides a solution aiming to change these current conditions.
Guarantees regarding cycle times and fluctuations in cycle times are prerequisite for a range of application fields in automation, including, for example, drive, control-, and conveyor technology. The data transfer times demanded in these application fields are significantly less than 1 ms. In addition to these applications requiring “hard” real-time capability, other applications such as process automation implement “soft” real-time capability with longer cycle times. Nevertheless guaranteed latencies are required for these applications as well.
Various real-time communication methods such as EtherCat or Profinet IRT have been specially developed to provide guaranteed cycle times. Although they are based on conventional Ethernet, they are not compatible with each other. This incompatibility has resulted in fragmented networks.
In most cases, traditional Ethernet networks involving automated sectors such as manufacturing are based on the hierarchical automation pyramid which separates information technology (IT) from operational technology (OT). IT includes classic office communication with typical end devices such as printers and personal computers. OT is made up of systems, machines and software used for process control and automation. The two areas are fundamentally different in how they communicate, with IT dependent on bandwidth and OT focused on high availability. Data traffic at the IT level is therefore often classified as non-critical while data traffic is designated (time-) critical at the OT level. As a result, each level uses a particular communication standard. While the Ethernet bus system with TCP/IP has largely prevailed at the IT level, various bus systems, also known as fieldbus systems, that particularly meet requirements for guaranteed latency times are widespread at the OT level. Each control vendor usually promotes a specific fieldbus system. For the user, this means that selecting the controller basically also determines the selection of the bus. The end user is thus often in a manufacturer's dependence, since the different bus systems are incompatible with each other
In the beginning, there were hardly any connections between IT and OT. Today, the continuous transmission of data is a fundamental necessity for digitized enterprises of all shapes and sizes. Consistent communication is essential to fulfill requirements demanded in operational data acquisition, remote access, or machine connection in the cloud. More importance will be placed on convergent, uniform networks in the future. Industrial automation is already undergoing a phase of restructuring based on the establishment of flexible and intelligent manufacturing, often described or already implemented in the context of Industry 4.0 or the Internet of Things (IoT). Smart production includes component parts, machines, and factories that are constantly communicating with one another in order to optimize and support processes in an automated way. These changes are also having an effect on the established automation model.
For the benefit of integration, the classic automation pyramid is being transformed into a broad network, which also includes sensors directly connected with higher control levels. The separation of field- and control levels is increasingly dissolving, creating the need for a uniform, convergent network in which critical data traffic can be simultaneously transmitted along with non-critical data traffic without negative reciprocal effects. The existing Ethernet must be adapted in order to meet these requirements. Sub-standards intended to enable converged critical and non-critical data traffic over a shared Ethernet infrastructure are therefore currently being defined and improved.
Advantages of TSN over traditional Ethernet include:
- Guaranteed latency times of real-time critical data throughout the network
- Critical and non-critical data traffic can be transmitted over a converged network
- Higher-level protocol layers can share a common network infrastructure
- Real-time control can also be applied outside of the OT area
- No vendor dependence
What is TSN?
Time-Sensitive Networking is a set of Ethernet sub-standards defined in the IEEE 802.1 TSN Task Group. TSN focuses on creating a convergence between information technology (IT) and industrial operational technology (OT) by extending and adapting existing Ethernet standards.
TSN technology aims to standardize features on OSI-Layer 2 in order that different protocols can share the same infrastructure. The challenge lies in configuring critical and non-critical data traffic so that neither real-time characteristics nor performance is impaired.
Important Core Elements
It is an essential prerequisite that all network equipment have the same understanding of time. All switches and terminals on the network must be time synchronized. Two different approaches to facilitate these functionalities are selectively used.
IEEE 1588-2008-Precision Time Protocol
Using an algorithm within the network, the IEEE 1588-2008 standard prompts the provision of the clock with the most accurate time to be designated to serve as Grandmaster Clock.
IEEE 802.1AS-2011 – Time
In addition to the general IEEE 1588 specification, the TSN Task Group adopted a special profile that stipulates the use of IEEE 1588 specifications in conjunction with IEEE 802.1Q. The profile was developed to facilitate implementations into applications that do not require the full functionality of the 1588-2008 standard. Because the profile did not meet all automation requirements, it was redesigned and is now known as IEEE 802.1AS-rev.
A second core functionality deals with the transmission of critical and non-critical data traffic within a converged network. Critical data traffic is guaranteed for delivery at a scheduled time while non-critical data traffic is usually given lower priority. Eight traffic classes already established according to IEEE 802 1Q are used to prioritize different types of data traffic. However, the standard's defined quality of service (QoS) was not designed for sending critical and non-critical data traffic in parallel. Due to buffer mechanisms in Ethernet switches, a low-priority Ethernet data packet can delay even those data streams with the highest priority along the transmission path. New prioritization mechanisms have been introduced to allow and regulate this coexistence. Depending on the application requirement, additional traffic shaper or scheduling mechanisms can be implemented. Below, two of these mechanisms are explained in more detail.
IEEE 802.1Qav – Credit Based Shaper
This standard defines an algorithm for data streams with real-time requirements to be prioritized over best-effort traffic. The Credit Based Shaper (CBS) was developed in 2009 by the IEEE 802.1 working group for the TSN Audio/Video Bridging (AVB) predecessor technology. The shaper assigns send credits to data streams. Data packets with reserved bandwidth are preferably transmitted as long as credit remains in the positive range. Send credits are spent during transmission until declining to a negative. Once a preferred transmission reaches a negative value, the best effort data packets next in line are transmitted. If this delays the forwarding of data packets with reserved bandwidth, credit is increased accordingly to allow prioritized Ethernet frames to be transmitted in succession following the best-effort traffic.
IEEE 802.1Qav – Time-Aware Scheduler
The basic function of the scheduler is to create equal discrete time periods (cycles). These cycles or time-slots are then assigned traffic classes. Time-aware shaping provides a fixed timetable for different data traffic classes to predetermine start and arrival times. This makes it possible to comply with defined transmission times and synchronize multiple data streams. Because the scheduler requires synchronization, all network participants know when which priority may be sent and processed. In addition to the time synchronization and various traffic shaping and scheduling mechanisms, other sub-standards have been or are currently in the process of being developed. These different standards are more a construction kit than an all-in-one solution. Modules can be combined in different variations to fulfill certain requirements of differing application scenarios, making it possible to adapt TSN networks to each particular one.
The Fraunhofer IPMS IP Core has currently implemented IEEE 802.1Qbv, IEE 802.1AS, IEEE 802.1Qav, and a real-time capable Media Access Control (MAC).
TSN IP Core on FPGA Basis
Due to the broad range of TSN functions, integration can best be realized on the basis of a field programmable gate array (FPGA). In comparison to integrated circuits (ICs) where many functionalities are predetermined, FPGA can be flexibly programmed. The logic gate (gate array) can be configured to generate complex digital functions. FPGAs advantages over ICs include:
- Significantly lower development costs
- Shorter implementation times
- Flexibly expandable and re-programmable
Because some TSN standards are currently still being revised and changed, the possibility to expand and re-program is a critical factor in implementation.
Summary and Outlook
Different real-time requirements demand different approaches. TSN lays the foundation to meet these requirements and the spectrum makes it possible to fulfill various latency, jitter and reliability requirements. Although the standardization process is not yet complete and the implementation of various standards is still in progress, core features can already be integrated into products. Changes or upgrades can be implemented subsequently with corresponding IP Core support services.
A TSN network achieves its full potential when all components and devices within the infrastructure are TSN compatible. Numerous manufacturers of industrial devices and switches are now working to make TSN-compatible products. During so-called “Plug Fests”, products from all manufacturers are tested for standards-compliant interoperability. Fraunhofer IPMS is currently testing its own TSN_CTRL IP-Core at the Industrial Internet Consortium (IIC) and Lab Network Industry 4.0 (LNI) Plug Fests. About Fraunhofer IPMS
Over 350 scientists and engineers from the Fraunhofer IPMS provide top services in applied research in the fields of industrial manufacturing and automation, medical technology, and improved quality of life. With an annual budget of more than 40 million euros, we create and develop customer-specific solutions using sensors, actuators, integrated circuits, wireless data communication and microelectronics. We focus on the sustainable success of our customers to understand and solve their individual challenges. Our partners rely on our innovation and system competences, from the first idea to transferring a solution to a series. Between two state-of-the-art cleanrooms and four development sites in Dresden, Cottbus, and Erfurt, we are developing innovative MEMS components and microelectronic parts on 200 and 300 mm wafers to complete whole systems. We maintain long-term relationships with all of our project partners. Certified according to ISO 9001, we are committed to a strict, indispensable customer orientation.