TSN-SW
Multiport TSN Ethernet Switch

The TSN-SW implements a highly flexible, low-latency, multiport TSN Ethernet switch. It supports Ethernet bridging according to the IEEE 802.1Q-2018 standard and implements the essential TSN timing synchronization and traffic-shaping protocols:

  • IEEE 802.1as,
  • 802.1Qav and 802.1Qbv,
  • 802.1Qbu and 802.1br, and
  • optionally the 802.1Qci and 802.1CB.

Featuring a configurable number of ports, the Layer-2 switch operates in cut-through mode at wire speed and can provide sub-microsecond port-to-port latency. The core is hence suitable for applications with demanding real-time requirements.

The TSN-SW operates efficiently under different usage scenarios and is highly configurable. Users can configure key factors via the core’s control registers:

  • the mapping of VLAN priority levels to TSN traffic classes,
  • the traffic scheduling and preemption parameters,
  • the treatment of special frames (i.e., broadcast, unknown, & internal), as well as
  • the VLAN ID and MAC lookup tables used for frame forwarding and filtering.

The host system can also switch the mode of operation of each individual port from cut-through to store-and-forward to eliminate the propagation of bad frames at the cost of increased latency. The core otherwise operates autonomously and only requires software assistance at runtime for correct time synchronization; a light-weight ptp/802.1AS software stack comes with the core for that purpose.

The TSN-SW uses standard AMBA® interfaces to ease integration. Its control and status registers are accessible via a 32-bit-wide APB bus, and packet data can be exchanged with the host system via AXI-Streaming interfaces with 32-bit data buses.

The TSN-SW is designed with industry best practices and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample synthesis and simulation scripts, an extensive testbench, and comprehensive documentation.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The TSN-SW has been rigorously verified, hardware-validated and tested in real-life environments.

It has also been tested and verified at TSN interoperability plugfests organized by the Labs Network Industry 4.0 (LNI 4.0) association and the Industrial Internet Consortium (IIC).
 

Deliverables

The core includes everything required for successful implementation:

  • Verilog RTL source code or targeted FFGA netlist
  • Testbenches
  • Sample Simulation and Synthesis scripts
  • Comprehensive Documentation
  • Lightweight PTP stack, easily portable to any other RTOS.

 

The TSN-SW can be mapped to any Intel FPGA device (provided sufficient silicon resources are available). The FPGA resources requirements depend on the core configuration. The following are sample results for a typical core configuration. Please contact CAST to get characterization data for your target configuration and technology.

Family/Device Configuration* ALMs Memory
(Mbits)
Cyclone V
5CSEBA6U19C6
64 Lookup Entries
4kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth
No Frame Preemption
17,692 0.83
Cyclone V
5CSEBA6U19C6
128 Lookup Entries
4kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth
Frame Preemption
26,838 1.62
Cyclone V
5CSEBA6U19C6
512 Lookup Entries
4kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth
Frame Preemption
33,306 2.60

*Partial list of configuration parameters

The TSN-SW can be mapped to any Xilinx FPGA device (provided sufficient silicon resources are available). The FPGA resources requirements depend on the core configuration. The following are sample results for a small number of core configurations. Please contact CAST to get characterization data for your target configuration and technology.

Family/Device Configuration* Logic Memory
Zynq UltraScale+
zu9eg-2-e
128 Lookup Entries
2kB Ingress Mem
4 Traffic Classes
1k TC Queue Depth
Frame Preemption
41,999 LUTs 65 RAMB36
28 RAMB18
Kintex 7
7k160t-1
256 Lookup Entries
16kB Ingress Mem
4 Traffic Classes
1k TC Queue Depth
No Frame Preemption
42,650 LUTs 65 RAMB36
28 RAMB18
Kintex UltraScale
ku115-2-i
256 Lookup Entries
16kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth
No Frame Preemption
42,330 LUTs 65 RAMB36
28 RAMB18
Kintex UltraScale+
ku15p-1-I
128 Lookup Entries
2kB Ingress Mem
4 Traffic Classes
1k TC Queue Depth
Frame Preemption
42,330 LUTs 65 RAMB36
17 RAMB18

*Partial list of configuration parameters

Related Content

Features List

Low-Latency & Flexible Ethernet Switch

  • Configurable number of 2 to 15 full-duplex Ethernet ports plus one internal port
    • More than 15 Ethernet ports available upon request
  • Layer-2, cut-through switching at wire speed
    • Store-and-forward mode can also be enabled per port at run time
  • Sub-microsecond port-to-port latency, in cut-through mode 10/100/1000 Mbps Ethernet speeds (2.5/10+ Gbps on request)
  • 802.1Q-2018 Tagged VLAN support
  • Port-based VLAN
  • Configurable VLAN-PCP to TSN-queue mapping (QoS by PCP)
  • Flexible VLAN and MAC forwarding & filtering
  • Configurable VLAN-ID & MAC lookup table for dynamic and static entries
  • Automatic aging table
  • Untagged ports support

TSN Features

  • Ready for IEEE 802.1as (lightweight software stack available)
  • Traffic shaping per IEEE 802.1Qav & IEEE 802.1Qbv with eight TSN-Queues
  • Frame preemption per IEEE 802.1Qbu and IEEE 802.3br
  • Frame Replication and Elimination for Redundancy per IEEE 802.1Qci
  • Per-Stream Filtering and Policing (PSFP) per IEEE 802.1CB 

Easy System Integration

  • AMBA™/AXI4 SoC Interfaces
    • 32-bit APB control/status interface
    • 32-bit AXI4-Stream for packet data
  • MII, GMII or RGMII, and MDIO Ethernet PHY interface per port
  • Requires minimal host assistance for initialization and operation
  • Provides a wide range of statistics via optionally instantiated counters
  • Complete reference designs available for Intel and Xilinx FPGA boards, including lightweight PTP stack sample application software

 

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