TSN-SE
TSN Ethernet Switched Endpoint Controller

The TSN-SE implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav and IEEE 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC.

The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. With cut-through switching and minimal buffering even at the Ethernet MAC level, the TSN-SE features extremely low and deterministic ingress and egress latencies, and simplifies the development of time-aware applications. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements, and provides the system with timing information (time-stamps, alarms, etc.) that is typically required for the operation of a TSN network bridge or endpoint.

The TSN-SE uses standard AMBA® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide APB bus, and packet data are input and output via AXI-Streaming interfaces with 32-bit data buses.  

The TSN-SE is designed with industry best practices, and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation. 
 

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The TSN-SE has been rigorously verified, hardware-validated and tested in real-life environments. Interoperability tested and verified within TSN plugfests organized by the Labs Network Industry 4.0 (LNI 4.0) association, and the Industrial Internet Consortium (IIC).
Deliverables

Deliverables

The core includes everything required for successful implementation:

  • Verilog RTL source code or targeted FPGA netlist
  • Testbenches
  • Sample Simulation and Synthesis scripts
  • Comprehensive Documentation
  • Lightweight PTP stack and device driver for FreeRTOS, easily portable to any other RTOS.
  • Linux device driver 

The TSN-SE can be mapped to any Intel FPGA device (provided sufficient silicon resources are available). The FPGA resources requirements depend on the core configuration. The following are sample results for a typical core configuration. Please contact CAST to get characterization data for your target configuration and technology.

Family/Device Configuration ALMs Memory
(Mbits)
Cyclone V
5CSEBA6U19C6
64 Lookup Entries
4kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth
No Frame Preemption
11,823 0.42
Cyclone V
5CSEBA6U19C6
128 Lookup Entries
4kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth
Frame Preemption
18,434 0.82
Cyclone V
5CSEBA6U19C6
512 Lookup Entries
4kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth
Frame Preemption
24,358 1.50

The TSN-SE can be mapped to any Xilinx FPGA device (provided sufficient silicon resources are available). The FPGA resources requirements depend on the core configuration. The following are sample results for a small number of core configurations. Please contact CAST to get characterization data for your target configuration and technology.

Family/Device Configuration Logic Memory
Kintex 7
XC7k325-2
64 Lookup Entries
16kB Ingress Mem
4 Traffic Classes
1k TC Queue Depth
No Frame Preemption
12,253 LUTs 30 RAMB36
22 RAMB18
Kintex 7
XC7k325-2
256 Lookup Entries
16kB Ingress Mem
4 Traffic Classes
1k TC Queue Depth
No Frame Preemption
14,922 LUTs 57 RAMB36
23 RAMB18
Kintex 7
XC7k325-2
64 Lookup Entries
16kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth
No Frame Preemption
17,941 LUTs 64 RAMB36
31 RAMB18
Kintex UltraScale
XCKU035-1-c
256 Lookup Entries
16kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth
No Frame Preemption
17,320 LUTs 64 RAMB36
31 RAMB18
Kintex 7
XC7k70t-1
128 Lookup Entries
2kB Ingress Mem
4 Traffic Classes
1k TC Queue Depth
Frame Preemption
23,533 LUTs 38 RAMB36
16 RAMB18
Kintex 7
XC7k70t-1
256 Lookup Entries
2kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth
Frame Preemption
31,858 LUTs 91 RAMB36
25 RAMB18
Kintex UltraScale
XCKU115-2-I
4k Lookup Entries
8kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth
Frame Preemption
78,176 LUTs 538 RAMB36
29 RAMB18

Related Content

Features List

TSN Ethernet Switched Endpoint

  • Two Ethernet ports & one host processor port
  • Suitable for daisy-chained networks such as rings

Low Latency & Flexible Switching

  • Low-latency Layer-2 Cut-Through Switching
  • Run-time switch configuration enables fast response to network changes
  • 802.1Q Tagged VLAN support
  • Port-based VLAN
  • Configurable VLAN-PCP to TSN-Queue Mapping (QoS by PCP)
  • Flexible VLAN and MAC forwarding & filtering
  • Configurable MAC lookup table for dynamic and static entries & automatic ageing table

TSN Features

  • Ready for IEEE 802.1AS (light-weight software stack available)
  • Traffic shaping per IEEE 802.1Qav & IEEE 802.1Qbv with eight TSN-Queues
  • Frame preemption per IEEE 802.1Qbu and IEEE 802.3br
  • IEEE 802-1AS-2020, 802.1CB, 802.1Qci & 802.1Qcc (coming soon)

Easy System Integration

  • AMBA™/AXI4 SoC Interfaces
    • 32-bit APB control/status interface
    • 32-bit AXI4-Stream for packet data
  • MII, GMII or RGMII, and MDIO Ethernet PHY interface per port
  • Requires minimal host assistance for its initialization and operation
  • Complete reference designs available for Altera and Xilinx, including lightweight PTP stack sample application software

Let's talk about your project and our IP solutions

Request Info