TSN-EP
TSN Ethernet Endpoint Controller

The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC.

The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. Requiring minimal software assistance for its initialization, it features extremely low and deterministic ingress and egress latencies, and simplifies the development of time-aware applications. The TSN-EP provides the system with timing information (time-stamps, alarms, etc.) that is typically required for the operation of a TSN network endpoint device. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements. 

The TSN-EP uses standard AMBA® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide APB bus, and packet data are input and output via 32-bit-wide AXI-Streaming buses.

The TSN-EP is designed with industry best practices, and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation. 

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The TSN-EP has been rigorously verified, hardware-validated, and tested in real-life environments. 

It has also been interoperability tested and verified within TSN plugfests organized by the Labs Network Industry 4.0 (LNI 4.0) association, and the Industrial Internet Consorti-um (IIC).

The TSN-VIP TSN Ethernet Verification IP package is also available, to help test the TSN-EP or an SoC containing it.

Deliverables

The core includes everything required for successful implementation:

  • Verilog RTL source code or targeted FPGA netlist
  • Testbenches
  • Sample Simulation and Synthesis scripts
  • Comprehensive Documentation
  • Lightweight PTP stack and device driver for FreeRTOS, easily portable to any other RTOS.
  • Linux device driver 

The TSN-EP can be mapped to any Intel FPGA device (provided sufficient silicon resources are available). The FPGA resources requirements depend on the core configuration. The following are sample results for a typical core configuration. Please contact CAST to get characterization data for your target configuration and technology.

Family/Device Configuration Logic Memory
Cyclone V
5CSXFC6D6F31C6<
8 Traffic Queues
1k Queue Depth
RTC, Traffic Shaper
Preemption
5,530 ALMs 389,320 bits

The TSN-EP can be mapped to any Lattice FPGA device (provided sufficient silicon resources are available). The FPGA resources requirements depend on the core configuration. The following are sample results for a typical core configuration. Please contact CAST to get characterization data for your target configuration and technology.

Family/Device Configuration Logic Memory
ECP3
LFE3-150EA
4 Traffic Queues
1k Queue Depth
RTC, Traffic Shaper
3,700 Slices
4 MULT18
10 EBR

The TSN-EP can be mapped to any Microsemi FPGA device (provided sufficient silicon resources are available). The FPGA resources requirements depend on the core configuration. The following are sample results for a typical core configuration. Please contact CAST to get characterization data for your target configuration and technology.

Family/Device Configuration Logic Memory
SmartFusion2
M2S090-std
4 Traffic Queues
1k Queue Depth
RTC, Traffic Shaper
6,835 4LUTs RAM64x18
RAM1K18

The TSN-EP can be mapped to any Xilinx FPGA device (provided sufficient silicon resources are available). The FPGA resources requirements depend on the core configuration. The following are sample results for a typical core configuration. Please contact CAST to get characterization data for your target configuration and technology.

Family/Device Configuration Logic Memory
Zynq-7000 SoC
zc7z020-1
2 Traffic Queues
1k Queue Depth
No RTC, No Traffic Shaper
No Preemption
2,000  LUTs 1 RAMB36
1 RAMB18
Zynq-7000 SoC
zc7z020-1
8 Traffic Queues
1k Queue Depth
RTC, Traffic Shaper
Preemption
6,154 LUTs 11 RAMB36
6 RAMB18

Related Content

Features List

Time Synchronization

  • Implements IEEE 802.1AS 
  • Grandmaster or Slave functionality
  • Highly accurate synchronization. Accuracy is typically in the order of few tens ns.
  • Provides the system with timestamps, periodic event triggers and alarm 

Traffic Shaping

  • Implements Traffic Scheduling as per IEEE 802.1Qav and IEEE 802.1Qbv
  • Implements Frame Preemption as per IEEE 802.1Qbu and IEEE 802.3br
  • Supports up to 8 traffic classes, as per VLAN (IEEE 802.1Q)
  • Enables bandwidth reservation and allocation per traffic class, and deterministic, low-latency, low-jitter communication for all traffic classes 
  • Enables high-precision synchronization in TSN networks
    • Egress latency: 
      10 Tx clock cycles
    • Ingress latency: 
      6 Rx clock cycles
  • 10/100/1000 Mbit/s Ethernet

Easy System Integration

  • AMBA/AXI4 Interfaces
    • 32-bit APB for control/status regis-ters
    • 32-bit AXI4-Stream for packet data
  • MII, GMII and RGMIII Ethernet PHY interface
  • Complete reference designs available for Altera and Xilinx, including sample application software
  • Requires minimal host assistance for its initialization

Verification IP

  • The TSN-VIP Ethernet Verification IP package is available for this core

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