LIN
LIN Bus Master/Slave Controller

Implements a communication controller that transmits and receives complete Local Interconnect Network (LIN) frames to perform serial communication according to the LIN Protocol Specification.

The LIN controller can be implemented as a master or as a slave and operate on LIN 1.3, 2.0, 2.1 or 2.2 LIN network. It uses a single master/multiple slave concept for message transfer between nodes of the LIN network. The message transfer can be controlled via a microcontroller interface and a LIN transceiver is needed for the connection to the LIN bus. 

The LIN core can be utilized for a variety of applications including;

  • low-cost automotive networks
  • interfaces for sensors and actuators

The core is a microcode-free design developed for reuse in ASIC and FPGA implementations. The scan-ready design is strictly synchronous with positive-edge clocking and no internal tri-states. The robustly verified core has been production proven multiple times.
 

The LIN core is partitioned into modules as shown in the block diagram.

Host Controller Interface
This interface is responsible for handling the communication with the host controller of the system.

Register Block
The Register Block provides control registers and status registers to control the LIN message transfer. Access to the registers is possible via the host controller interface.

Data Buffer
The 8-byte Data Buffer stores the data that has to be sent with the current LIN frame or the data that has been received with the last LIN frame. Access to the Data Buffer is possible via the host controller interface.

Control FSM
The finite control state machine is responsible for the behavior of the core depending on host controller commands and bus activity. It generates and processes the LIN frame fields according to the LIN protocol. 

Bit Stream Processor
This module converts the data stream from parallel to serial (from transmit buffer to bus) and from serial to parallel (from bus to receive buffer).

Bit Timing Logic
The Bit Timing Logic is responsible for synchronizing the received data stream from the bus with the internal bit time clock.

Core Modifications

The LIN core can be modified to include an acceptance filter. With that, a simple LIN slave that transmits response frames for only one identifier could be realized without the assistance of a host controller. Please contact CAST, Inc. directly for any required modifications.

Verification

The core has been verified through extensive synthesis, place and route, and simulation runs. It has been embedded in several shipping customer products, and is proven in both ASIC and FPGA technologies.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, expected results, synthesis scripts and comprehensive user documentation.
 

The LIN can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample ASIC performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

ASIC Technology

Configuration

Approx. Area

Frequency

TSMC 0.18 Master 2,710 gates 4 MHz
TSMC 0.18 Slave 3,840 gates 4 MHz
TSMC 0.18 Slave w/ auto bit rate 4,060 gates 4 MHz
TSMC 0.13 Master 2,500 gates 4 MHz
TSMC 0.13 Slave 3,500 gates 4 MHz
TSMC 0.13 Slave w/ auto bit rate 3,760 gates 4 MHz

Note: 4 MHz is the required LIN speed.

 

Intel GPGA logo

The LIN can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample Altera results. Please contact CAST to get characterization data for your target configuration and technology.

Family / Device Mode

Logic

Resources

Fmax2

(MHz)

Arria 10

10AS016C3U19I2LG
Master 228 ALMs 446
Slave1 361 ALMs 297

Cylcone 10 LP

10CL010YU256C6G
Master 492 LEs 187
Slave1 833 LEs 161

Max 10

10M08DAF484I7G
Master 497 LEs 148
Slave1 811 LEs 141

Notes:
1) Slave implemented with clock synchronization
2) Working frequency of LIN controller is 4 MHz

Lattice Semiconductors logo

The LIN core can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following are sample implementation data for the core assuming all I/Os are routed off-chip. Please contact CAST to get characterization data for your target configuration and technology.

Family

Device Config

Logic

Fmax2

(MHz)
MachXO2
7000HC-5
Master
269 Slices
536 LUT4s
68
MachXO2
7000HC-5
Slave1
419 Slices
836 LUT4s
55

Notes:
1) Slave implemented with clock synchronization
2) Working frequency of LIN controller is 4 MHz

Microsemi logo

The LIN can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Microsemi Device Configuration Cells RAM Blocks FMAX
(MHz)
Sequ (R) Comb (C)
ProASIC3
A3P1000-2
Master 209 773 - 4
ProASIC3
A3P1000-2
Slave 249 1066 - 4
ProASIC3
A3P1000-2
Slave w/ auto bit rate 269 1262 - 4
SmartFusion2
M2S150-STD
Master 209 DFF 488 4LUT - 4
SmartFusion2
M2S150-STD
Slave 288 DFF 755 4LUT - 4
Igloo2
M2GL150-STD
Master 209 DFF 488 4LUT - 4
Igloo2
M2GL150-STD
Slave 318 DFF 887 4LUT - 4

Note: 4 MHz is the required LIN speed.

Xilinx Program logo

The LIN can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample Xilinx performance and resource utilization data assuming all I/Os are routed off-chip. Please contact CAST to get characterization data for your target configuration and technology.

Family
Device LUTs Fmax (MHz)2
Master Slave1
Spartan-7
xc7s50-2 333 581 197
Artix-7
xc7a15t-3 341 597 222
Kintex-7
xc7k160t-3 348 601 263
Virtex-7
xc7vx485t-3 349 597 333
Kintex-Ultrascale
xcku035-3-e 333 595 357
Virtex- Ultrascale
xcvu080-3-e 355 607 454
Kintex-Ultrascale+
xcku13p-3-e 359 611 526
Virtex- Ultrascale+
xcvu13p-3-e 355 606 588

Notes:
1) Slave implemented with clock synchronization
2) Working frequency of LIN controller is 4 MHz

Related Content

Features List

  • Support of LIN specification 2.0, 2.1, and 2.2A
    • Backwards compatible with LIN specification 1.3
  • Configurable for support of master or slave functionality
  • Programmable data rate between 1 Kbit/s and 20 Kbit/s (for master)
  • Automatic bit rate detection (for slave)
  • 8-byte data buffer
  • Generic 8-bit microcontroller interface
    • Wrappers converting the generic microcontroller interface to AMBA APB or AHB are offered with the core
  • Slave can be implemented with or without clock synchronization
  • Fully synchronous design, available in VHDL or Verilog, completely synthesizable
  • The LIN Controller synthesizes to approximate 2500 to 3800 gates depending on the configuration
  • Robustly verified and multiple times production proven IP core
  • LIN Verification IP is available to use with this core

Resources

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