Silicon IP Cores
JPEG & JPEG-LS Image Compression
Encoders, Decoders, Reference Designs, and more for images & video
This IP Family offers a set of efficient hardware encoders and decoders for Lossy compression with JPEG and Lossless compression with JPEG-LS.
This family covers a wide range of applications, supporting inputs up to UHD resolution and various image sensor input formats. These cores are also available integrated in subsystems with other CAST IP cores to streamline the entire communications channel, providing a fast hardware implementation and cutting development time.
With over two decades of imaging IP experience, CAST engineers become an integral part of the design team, helping to architect systems that optimally meet the challenges of compression quality and performance, hardware implementation, power consumption, latency, and cost.
Over 100 CAST image compression customers span the consumer electronics, automotive, aerospace, defense, industrial, and medical industries. They have all demanded high-quality, easy-to-implement, low-risk IP, and have successfully shipped millions of products using these cores and subsystems.
The Encoder and Decoder IP cores offer:
Scalable performance supporting resolutions beyond Ultra-High Definition (UHD) and/or ultra-high frame rates.
Extremely small silicon footprint, enabling low-power and economical implementations in FPGAs and ASICs.
Excellent quality with high performance lossless compression and superior rate control for low-bandwidth lossy compression applications.
Read about the family below, follow the links to individual product pages, and contact Sales to learn more or discuss how we can support your evaluation.
Each encoder and decoder in the family satisfies particular needs for performance, power consumption, and silicon area, and offers smart tradeoffs of compression degree and quality.
JPEG and Motion JPEG Encoders and Decoders in Baseline and Extended (12-bit) versions available as economically small and easy to implement cores. Built-in hardware implementations of Raster to Block Conversion and Block to Raster Conversion remove the requirement for a frame buffer to perform these operations.
JPEG-LS Encoder and Decoder cores that provide lossless compression of similar or superior efficiency to those obtained with more advanced algorithms such as JPEG2000.
Motion JPEG Over IP Subsystems that offer complete hardware implementations of image communication pipelines to enable the rapid development of image streaming applications. The subsystems add to the encoder or decoder core to further offload the CPU and reduce power requirements. Two pre-integrated networking options are available:
UDP/IP hardware protocol stack for high-speed communication over a LAN or a point-to-point connection for speeds up to 100Gbps.
RTP Real Time Transport Protocol hardware stack that encapsulates/decapsulates JPEG streams to RTP packets.
Great Image Compression in Lower-Cost Silicon
The small size, low power consumption, and high performance of these cores make it easy and cost-effective to add image processing to almost any product category.
Very Low Power Consumption
These dedicated hardware encoders and decoders use dramatically less power than any software or hardware/software codecs with similar capabilities.
They are all designed to use minimal silicon area, and their smaller footprint further saves energy over larger cores.
High Performance, 4K/8K Processing
Energy saving doesn’t come at the expense of processing power. The throughput of the encoders and decoders can readily scale to handle 4K, 8K, or higher frame sizes and high frame rates, even in modest FPGAs.The JPEG encoders run ultra-fast, processing up to 32 samples/cycle and easily handling up to UHD/4K video in FPGAs. Multi-channel support and multiple cores are options for the most demanding systems.
The Most Efficient High-Resolution Solutions
The Motion JPEG capabilities of the image encoders and decoders offers by far the most economical way to process up to 4K video. Yet for moderate compression levels, they provide video quality that’s practically equal to much larger and more complex H.264, H.265, or JPEG2000 encoders.
The result? These JPEG cores let you encode UHD/4K video even in smaller ASIC silicon or extremely modest FPGAs. Their scalability gets you to even higher resolutions, still with great economies.
These image compression encoders and decoders operate in standalone mode.Once programmed, they function autonomously, with no need for software control or interaction with the system processor (a further energy savings).
The JPEG and JPEG-LS cores use industry-standard ARM® AMBA® interfaces for easy SoC compatibility.
The JPEG cores use the AMBA® AXI4-Stream interface for pixel and stream data, and APB or AXI4-Lite for register access. Optional Raster Conversion further simplifies integration via an AXI interface to the lines buffer for easy connection to on- or off-chip memory. An optional AHB wrapper for the JPEGs includes a DMA controller.
Efficient, Adaptable Memory Interfaces
The cores’ memory interfaces also ease integration challenges and reduce system-wide power consumption.
The JPEG cores can handle processing without accessing energy-consuming off-chip memory. It is only in the case of high-resolution video, where users may choose to use an external memory for the buffering required by the Raster-Conversion functions.
To ease integration and enable the use of shared-memory resources, the Raster Conversion functions are tolerant to memory access latency, independent of memory type, and operate on a different clock than the memory device.
Evaluate JPEG cores before buying or get a head start on system development with our pre-integrated platforms for JPEG. Each combines compression cores with peripherals, interconnects, and essential software in ready-to-run FPGA board systems.
Motion-JPEG over IP Subsystems and Boards
Our off-the-shelf Motion JPEG Over IP Subsystem makes it especially easy to build in image compression over Ethernet or Wi-Fi. It includes a JPEG encoder core and everything needed to exercise it, including UDP/IP, RTP, and DMA controllers. Ready-to-run board kits are available for Intel or Xilinx; see the Motion JPEG Over IP product page for all the details:
Compare jPEG Encoders and Decoders in this table of specification and features.