AES-CCM
AES-CCM Authenticated Encrypt/Decrypt Engine

The AES-CCM encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. 

Two architectural versions are available to suit system requirements. The Standard version (AES-CCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-CCM-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block.  

CCM stands for Counter with CBC-MAC mode. CCM is a generic authenticate-and-encrypt block cipher mode. CBC-MAC is utilized to generate an authentication string while CTR mode is used to encrypt. 

The AES-CCM core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.  
 

An AES encryption operation transforms a 128-bit block into a block of the same size. The encryption key can be chosen among three different sizes: 128, 192, or 256 bits. The key is expanded during cryptographic operations.  

The AES algorithm consists of a series of steps repeated a number of times (rounds). The number of rounds depends on the size of the key and the data block. The intermediate cipher result is known as state. Initially, the incoming data and the key are added together in the AddRoundKey module. The result is stored in the State Storage area.

Number of rounds as a function of key size
  KSIZE = 00 KSIZE = 01 KSIZE = 10
Rounds 10 12 14

The state information is then retrieved and the ByteSub, Shiftrow, MixColumn and AddRoundKey functions are performed on it in the specified order. At the end of each round, the new state is stored in the State Storage area. These operations are repeated according to the number of rounds.  

The final round is anomalous as the MixColumn step is skipped. The cipher is output after the final round. 

CCM mode 

During encryption, CBC-MAC is used to process the message data and additional data to produce an authentication value T. This is then encrypted using CTR mode. CTR mode is also used to encrypt the message. The output is an encrypted message and an encrypted authentication string U. 

During decryption, the above steps are reversed. The message is decrypted first with CTR mode. The resulting decrypted message is processed, together with the additional data with CBC-MAC in order to produce the encrypted authentication string U. If the latter is different from the original U, the authentication has failed. In this case no other information (i.e. no decrypted data or the value of the authentication string) should be revealed except the failure itself. 

Key Expansion 

The AES algorithm requires an expanded key for encryption or decryption. The KEXP AES key expander core is available as an AES-CCM core option. 

During encryption, the key expander can produce the expanded key on the fly while the AES core is consuming it. For decryption, though, the key must be pre-expanded and stored in an appropriate memory before being used by the AES core.  This is because the core uses the expanded key backwards during decryption. 

In some cases a key expander is not required. This might be the case when the key does not need to be changed (and so it can be stored in its expanded form) or when the key does not change very often (and thus it can be expanded more slowly in software). 

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven both in ASIC and FPGA technologies. 
 

Support 

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. 


Deliverables 

The core is available in ASIC (RTL) or FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes 

  • HDL RTL source 
  • Sophisticated HDL Testbench (self checking) 
  • Simulation script, vectors & expected results 
  • Synthesis script 
  • User documentation 

The AES-CCM can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES-CCM Standard Core ASIC Implementation Results

ASIC Technology

Number of eq. gates

Fmax (MHz)

Throughout (Gbps)

TSMC 16nm
6,267
500
1.455
TSMC 28nm HPM
6,060
500
1.455

TSMC 40nm G

7,374
500
1.455

Throughput for a 128-bit key size

AES-CCM Fast Core ASIC Implementation Results

ASIC Technology

Number of eq. gates

Fmax (MHz)

Throughout (Gbps)

TSMC 16nm
15,202
500
5.818
TSMC 28nm HPM
14,905
500
5.818

TSMC 40nm G

18,382
500
5.818

Throughput for a 128-bit key size

The AES-CCM can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Intel results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core.Please contact CAST to get characterization data for your target configuration and technology.

AES-CCM Standard Core Intel Implementation Results

Family

ALMs

RAM bits

Freq. (MHz)

Throughout (Mbps)

Arria 10 GX (-2)
482
0
150
436
Stratix V (-1)
518
0
200
582
MAX 10 (-7)
1,432
16
75
218

Throughput for a 128-bit key size

AES-CCM Fast Core Intel Implementation Results

Family

ALMs

RAM bits

Freq. (MHz)

Throughout (Mbps)

Arria 10 GX (-2)
1,724
0
100
1,164
Stratix V (-1)
1,682
0
200
2,327
MAX 10 (-7)
4,502
0
75
873

Throughput for a 128-bit key size

The AES-CCM can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Xilinx results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

AES-CCM Standard Core Xilinx Implementation Results

Family

LUTs

BRAMs

Freq. (MHz)

Throughout (Mbps)

Virtex-7 (-3)
681
0
300
873
Kintex-7 (-2)
664
0
150
436
Kintex UltraScale+ (-1)
458
2
200
582
Kintex UltraScale (-2)
672
0
250
727
Kintex UltraScale+ (-1)
457
2
400
1,164

Throughput for a 128-bit key size

AES-CCM Fast Core Xilinx Implementation Results

Family

LUTs

BRAMs

Freq. (MHz)

Throughout (Mbps)

Virtex-7 (-3)
1,478
0
300
3,491
Kintex UltraScale (-1)
812
8
200
2,326
Kintex UltraScale (-2)
1,460
0
250
2,908
Kintex UltraScale+ (-1)
832
8
400
4,652

Throughput for a 128-bit key size

Related Content

This product is sourced from Technology Partner Ocean Logic.

Features List

  • Encrypts  and decrypts using the AES Rijndael Block Cipher Algorithm
  • Satisfies  Federal Information Processing Standard (FIPS) Publication 197 from the US  National Institute of Standards and Technology (NIST)
  • Processes  128-bit data in 32-bit blocks
  • Employs  user-programmable key size of 128, 192, or 256 bits
  • Two  architectural versions:
    • Standard is more compact: 32-bit data path size
      Processes each 128-bit data block in 44/52/60 clock cycles for 128/192/256-bit  cipher keys, respectively
    • Fast yields higher transmission rates: 128-bit data path
      Processes each 128-bit block in 11/13/15 clock cycles for 128/192/256-bit cipher keys, respectively
  • NIST Certified
  • Works with a pre-expended key or can integrate the optional key expansion function
  • Simple, fully synchronous, reusable design
  • Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices

Resources

NIST: Approved Block Ciphers

FIPS 197, Advanced Encryption Standard (AES): download PDF

AES test suite: The Advanced Encryption Standard Algorithm Validation Suite (AESAVS): download PDF

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This core implements encryption functions and as such it is subject to export control regulations. Export to your country may or may not require a special export license. Please contact CAST to determine what applies in your specific case.