Commercially proven AES encryption and decryption engines now certified to meet standard for function and interoperability.
Silicon IP Cores
Enables easy implementation of small, low-power, low-latency TSN Ethernet nodes for daisy-chained or ring networks.
Low-latency Video Decoding IP Subsystem Meets Megh's Requirements for Video Analytics System Using AI/Deep Learning to Prevent Retail Inventory Loss
APB Subsystem
AXI to APB Bus Bridge
AHB Subsystem
AXI Subsystem
SPI to AHB-Lite Bridge
ASIC and FPGA IP core is ready to reduce development time and risk for automotive system designers using Time Sensitive Networking (TSN) Ethernet.
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