Reduce bandwidth and storage requirements with standard GZIP/ZLIB/Deflate compression at over 90Gbps on Xilinx Alveo Data Center Accelerator Cards.
Silicon IP Cores
Commercially proven AES encryption and decryption engines now certified to meet standard for function and interoperability.
ASIC and FPGA IP core is ready to reduce development time and risk for automotive system designers using Time Sensitive Networking (TSN) Ethernet.
New 100Gbps UDP/IP core: lean networking protocol stack gets 512-bit datapath to increase communication speed, offloads UDP/IP functions from processor to improve system performance.
CAST's proven HDLC/SDLC protocols controller IP core gets improved error resiliency and DAL-A Certification Data Package to simplify standard conformance for safety-critical avionics developers.
New MIPI I3C Basic controller includes I3C-to-AHB Bridge and provides fast, low-power, royalty-free interface for connecting sensors and peripherals to processors.
LTX cameras by Baumer, Ltd. use CAST JPEG IP cores, reducing bandwidth, CPU load, and required storage capacity while simplifying the camera system design and lowering integration cost.
The EMSA5-FS is a 32-bit, 5-stage pipelined RISC-V ISA compatible embedded processor with built-in functional safety features and deliverables making it ready for ISO 26262 ASIL-D certification.
半导体知识产权提供商CAST, Inc.今天宣布立即推出EMSA5-FS，这是一种容错嵌入式RISC-V处理器IP核，旨在满足汽车、机载和其他安全关键应用的最严格的功能安全要求。
Get expert advice on the benefits and trade-offs of GZIP, LZ4, Snappy, and Zstd compression methods and IP cores for implementing them in this CAST Lossless Data Compression webinar.