UART with FIFOs and Synchronous CPU Interface
Silicon IP Cores
SHA-3 Secure Hash Crypto Engine
A full-featured, combined I2C and SPI serial communications interface controller IP core that saves silicon resources and development effort versus using two separate IP cores.
I2C and SPI Master/Slave Controller
I2C & SMBus Controller
Smart Card Reader Controller
Message Digest Algorithm Processor
AXI4 to/from AXI4-Stream Scatter-Gather DMA
AXI4 to/from AXI4-Stream DMA
Octal SPI Master/Slave Controller