AXI to APB Bus Bridge
Silicon IP Cores
AHB Subsystem
AXI Subsystem
SPI to AHB-Lite Bridge
ASIC and FPGA IP core is ready to reduce development time and risk for automotive system designers using Time Sensitive Networking (TSN) Ethernet.
Real-Time Clock with APB Interface
Timer/Counter with APB Interface
Watchdog Timer with APB Interface
100G UDP/IP Hardware Protocol Stack
New 100Gbps UDP/IP core: lean networking protocol stack gets 512-bit datapath to increase communication speed, offloads UDP/IP functions from processor to improve system performance.