Tiny Baseline JPEG Encoder
Silicon IP Cores
AVC/H.264 Video Encoder with Compressed Frame Store
Reduce bandwidth and storage requirements with standard GZIP/ZLIB/Deflate compression at over 90Gbps on Xilinx Alveo Data Center Accelerator Cards.
Low-latency Video Decoding IP Subsystem Meets Megh's Requirements for Video Analytics System Using AI/Deep Learning to Prevent Retail Inventory Loss
LTX cameras by Baumer, Ltd. use CAST JPEG IP cores, reducing bandwidth, CPU load, and required storage capacity while simplifying the camera system design and lowering integration cost.
CAST offers 32-bit RISC-V Processor cores focused on Functional Safety -- with an ISO 26262 ASIL D ready certification package — and ultra-low-power embedded applications — providing competitive performance with remarkably low power and area usage.
32-bit Embedded RISC-V Functional Safety Processor
The EMSA5-FS is a 32-bit, 5-stage pipelined RISC-V ISA compatible embedded processor with built-in functional safety features and deliverables making it ready for ISO 26262 ASIL-D certification.
半导体知识产权提供商CAST, Inc.今天宣布立即推出EMSA5-FS，这是一种容错嵌入式RISC-V处理器IP核，旨在满足汽车、机载和其他安全关键应用的最严格的功能安全要求。
Simplify your ISO 26262 Functioonal Safety certification effort by using IAR's certified Embedded Toolkit for RISC-V with the EMSA5-FS processor.