IP core provides easy integration of up to seven CAN buses with an Ethernet network in automotive and industrial systems; will be shown at TSN/A Conference.
Silicon IP Cores
Enables easy implementation of small, low-power, low-latency TSN Ethernet nodes for daisy-chained or ring networks.
Low-latency Video Decoding IP Subsystem Meets Megh's Requirements for Video Analytics System Using AI/Deep Learning to Prevent Retail Inventory Loss
ASIC and FPGA IP core is ready to reduce development time and risk for automotive system designers using Time Sensitive Networking (TSN) Ethernet.
100G UDP/IP Hardware Protocol Stack
New 100Gbps UDP/IP core: lean networking protocol stack gets 512-bit datapath to increase communication speed, offloads UDP/IP functions from processor to improve system performance.
In this column, security and real-time performance are indispensable for networks required in the IoT era. As one solution, we will introduce TSN, which is a new network standard that gives Ethernet real-time performance. (In Japanese, with link to...
10G/25G UDP/IP Hardware Protocol Stack
The CAST UDPIP core implements a UDP/IP hardware protocol stack that enables high-speed communication over an Ethernet Link. Besides the UDP and IPv4, there are also additional protocols implemented in the core (ARP/ICMP/IGMP/DHCP). The UDPIP core...
Time-Sensitive Networking (TSN) Ethernet endpoint controller cores gain Frame Preemption for highly-demanding real-time operation and a Linux Driver for easier Linux system development.