Watchdog Timer with APB Interface
Silicon IP Cores
Error Correcting Code for SRAMs
AXI4 to/from AXI4-Stream DMA
Pulse Width Modulator
New multichannel digital audio interface IP core supports I2S and TDM interfaces and is highly configurable to suit nearly any application.
Hardware cores for a variety of standard interface protocols: I2C, SPI, UARTs, and HDLC/SDLC.
Pre-Integrated AMBA bus-fabric & peripherals subsystems
A set of controller IP cores for different types of memories, including Serial/SPI Flash, Cache Memory, and SRAM.
I2C and SPI Master/Slave Controller
A full-featured, combined I2C and SPI serial communications interface controller IP core that saves silicon resources and development effort versus using two separate IP cores.