经验证的质量、低风险、广泛的生态系统和卓越的技术支持使CAST的8051成为许多系统功能的经济高效的解决方案
半导体知识产权提供商CAST今天宣布,杭州晶华微电子股份有限公司——一家领先的模拟混合信号集成电路设计和无晶圆厂半导体供应商——已从CAST获得8051微控制器IP核,用于目前正在开发的一套新芯片。
...The R8051XC2 configurable processor core implements a range of fast, 8-bit, micro-controllers that execute the MCS®51 instruction set.
The IP core runs with a single clock per machine cycle, and requires an average of 2.12 machine cycles per instruction. Dhrystone 2.1 tests show it to run from 9.4 to 12.1 times faster than the original 8051 at the same frequency. Representative 40 nm ASIC results have reached 1.2 GHz, for an effective speed up of 1,200 times over 80C51 chips.
The core has a rich set of optional features and peripherals. Designers can choose from several versions, including the easy-to-configure full version with all options included; a custom, non-configurable version with options specified at purchase; and pre-packaged versions with different sets of options and degrees of configurability.
All versions of the core benefit from power-saving architectural efficiency—the R8051XC2 is 10% better in milliwatts/DMIP than our previous generation—and various power-management options are available. System development is facilitated through a native on-chip debugging option and support by development tools from Keil and IAR.
This product builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. Designed for easy reuse in ASICs or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional debug & SPI modules), synchronous reset, and no internal tri-states. Representative 40nm ASIC results show the core to be conservative in its use of space, requiring just 7,200 to 35,500 gates (DMA not included).
The core’s architecture eliminates redundant bus states and implements parallel processing of fetch and execution phases. Since a cycle is aligned with memory fetch when possible, most of the 1-byte instructions are performed in a single cycle.
The core uses one clock per cycle. This, together with other extensions (multi-DPTR, MDU), leads to significant performance improvements with respect to the original Intel device operating with the same clock frequency.
The Dhrystone 2.1 benchmark score varies from 0.088 to 0.114 DMIPS/MHz, which translates to speed improvements from 9.4 to 12.1 times over the standard 80C51, or 1200 times the maximum performance at 1.2 GHz in 40nm technology.
Sample Dhrystone 2.1 benchmark results are as follows.
Configuration |
DMIPS/MHz |
80C51 Speed Ratio |
Basic |
0.0883 |
9.4 |
Multiple DPTR |
0.1020 |
10.9 |
Multiple DPTR+auto-inc |
0.1111 |
11.8 |
MDU+Multiple DPTR+auto-inc |
0.1136 |
12.1 |
Three versions of the core are available, offering a range of capabilities and prices.
ASIC (RTL) and FPGA (netlist) deliverables are available; FPGA packages are not user-configurable.
The native debugging package is an extra option for all versions.
The core has been verified through extensive synthesis, place and route, and simulation runs. It has been embedded in numerous shipping customer products, and is proven in both ASIC and FPGA technologies.
The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation. ASIC versions include:
The R8051XC2 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample results using a 90nm ASIC technology, and separate optimizations for speed and area. The EASE debug option is not included. Please contact CAST to get characterization data for your target configuration and technology.Reference designs have been evaluated in a variety of technologies.
Version & Configuration | Maximum Speed | Minimum Area |
---|---|---|
R8051XC2-CPU (CPU – only) |
1209 MHz | 7.2k gates |
(CPU + peripherals + OCDS) | 780 MHz | 35.5k gate +1.5K per DMA channels |
Full user-configurable version includes all of these; other versions include a subset (see Versions).
Code and debug this 8051 with these popular IDEs:
IAR Systems Embedded Workbench for 8051
These tools work with an optional, native on-chip debug block and inexpensive external adapter (pod) with a JTAG four-wire or SWAT Single-Wire PC interface.
Easily evaluate this 8051's features and performance in your own environment with the
Talos Series Evaluation Kit for 8051s.
Understanding Interrupt Latency in Modern 8051s
by Nikos Zervas at ChipEstimate.com