UDPIP-10G/25G
10G/25G UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 25Gbps  even in processor-less SoC designs. 

Trouble-free network operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address, etc). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity.  It can use a static IP address or automatically request and acquire an IP address from a Dynamic Host Configuration Server (DHCP) server. Furthermore, the core supports 801.1Q tagging and is suitable for operation in a Virtual LAN.

The core is easy to integrate into systems with or without a host processor. Packet data can be read/written to the core via dedicated AMBA® AXI4-stream or Avalon®-ST interfaces, while registers are accessible via an AXI4-Lite, or AHB or Avalon-MM slave interface. Bridges to other interface protocols can be made available upon request. The core is Ethernet MAC-independent but can be made available pre-integrated with an Altera, Xilinx, or other third-party eMAC core.

The UDPIP-10G/25G core receives and transmits UDP packet data, and forwards other traffic from the Ethernet MAC to the application and vice versa. It also receives and transmits ARP requests and responses, and responds to ICMP echo reply messages. The core generates and validates the UDP and IP checksums of outgoing and incoming packets, respectively. It can be programmed to discard or forward corrupted packets to the user application.

The core consists of the following modules:

The Ethernet Frame Decoder receives Ethernet frames from an external Ethernet MAC, detects the frame type, and sends frames to the ARP or the IP packet decoder. The Ethernet Frame Transmitter provides the external Ethernet MAC interface. The transmitter also multiplexes ARP and IP transmit packets from the core subsystems.

The VLAN Receiver receives Ethernet frames from an external Ethernet MAC, and when enabled detects and compares VLAN tag & filters frames to the correct VLAN tag. The VLAN Transmitter receives Ethernet frames from the Ethernet Frame Transmitter and adds the VLAN Tag to the frames when enabled. 

The Packet Receiver Module receives IP packets and handles them according to the packet type. The Packet Decoder receives IP packets and the decoded packets are stored in the Rx Packet Buffer and then passed to the user application.  The Received Packet Buffer implements separate data storage for the UDP application data and other data, and its size is configurable at synthesis time.

The Packet Transmit Module assembles UDP and ICMP packets. The UDP application data, as well as the ICMP packet data, are stored in the transmit buffer, the size of which is configurable at synthesis time.

The ARP Module sends and receives ARP packets and handles the packets according to command in the packet. The DHCP Module automatically requests and acquires an IP address from a DCHP server.

The UDP Channel Demultiplexer receives UDP packets and demultiplexes them according to a decoded UDP channel number. The UDP Channel Multiplexer receives UDP packet channels from a user application and multiplexes them to the Packet Transmitter module.

Finally, the Control and Status Registers control the core functionality and report the core status

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in synthesizable RTL and FPGA netlist forms and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts, and comprehensive user documentation.

The UDPIP-10G/25G is a purely digital design that does not use any technology-specific modules and can, therefore, be mapped to any ASIC technology. The following table provides sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The sample results do not represent the highest speed or smallest area for the core. Please contact CAST to get characterization data for your target configuration and technology.

UDP
Channels
ASIC
Technology
Eq. NAND2
gates
Fmax
(MHz)
Memory
(Bytes)
Ethernet
Speed
1 TSMC 65nm 39,181 391 33,024 1, 10, and 25 Gbps.
1 TSMC 90nm 36,961 391 33,024 1, 10, and 25 Gbps.
4 TSMC 65nm 48,528 391 49,408 1, 10, and 25 Gbps.
4 TSMC 90nm 45,625 391 49,408 1, 10, and 25 Gbps.

Table 1: UDPIP-10G/25G sample results for the core configured with ARP, ICMP, IGMP, Rx and Tx, and without DHCP and VLAN support

The UDPIP-10G/25G can be mapped to any Intel FPGA device (provided sufficient silicon resources are available). The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Family UDP Channels ALMs Fmax (MHz) Memory Bits
Cyclone 10 GX
10CX085YF672E5G
1
4
3,922
5,391
191
180
198,656
346,112
Arria 10
10AX115S2F45E1SG
1
4
3,773
5,246
196
192
198,656
346,112
Stratix 10
1SG085HN3F43E3VG
1
4
4,142
5,786
228
234
198,656
346,112

Table 1: UDPIP-1G sample results for the core configured with ARP, ICMP, IGMP, 16kB Rx Buffers, 8kB Tx Buffers, and without DHCP and VLAN support

The UDPIP-10G/25G can be mapped to any Xilinx FPGA device (provided sufficient silicon resources are available). The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Family
Device
UDP
Channels
LUTs BRAM
Tiles
Fmax
(MHz)
Ethernet
Speed
Kintex U
xcku025-1
1 4,999 6 156,250 10/100/1000
and 10G
4 6,299 10
Kintex UP
xcku9p-1
1 4,957 6
4 6,258 10
Kintex UP
xcku9p-2
1 4,855 6 390.625 10/100/1000,
10G, and 25G
4 6,199 10

Table 1: UDPIP-10G/25G sample results for the core configured with ARP, ICMP, IGMP, 16kB Rx buffers, 8kB Tx buffers, and without DHCP and VLAN support

This core is part of CAST’s family of UDP/IP IP cores. These cores operate without any processor assistance and implement the UDP, IPv4, ARP, ICMP, IGMP, and DHCP protocols. However, CAST’s UDP/IP cores do not embed an Ethernet MAC module, and therefore do not control, depend on, nor determine the Ethernet link speed. They do feature different data-path and interface bit-widths making each UDP/IP core more suitable for specific Ethernet link speeds as shown in the following table:

Core name Data-path Data-path Required System Clock Freq. [MHz]
1Gbps 10Gbps 25Gbps 40Gbps 50Gbps 100Gbps
UDPIP-1G 32-bit 31.25 312.5 X X X X
UDPIP-10G/25G 64-bit 15.625 156.25 390.625 X X X
UDPIP-40G/50G 256-bit - 60 147 235 292 X
UDPIP-100G 512-bit - - - 156.25 195 322

Related Content

Features List

Complete UDP/IP Hardware Stack

  • 10/100/1000, 10G, and 25G Ethernet 
  • IPv4 support without packet fragmentation
  • Jumbo and Super Jumbo Frames
  • Transmit and Receive 
  • ARP with Cache
  • ICMP (Ping Reply)
  • IGMPv3 (Multicast)
  • UDP/IP Unicast and Multicast 
  • UDP Port Filtering
  • UDP/IP Checksums generation and validation, and optional Ethernet CRC validation
  • VLAN (IEEE 802.1Q) support
  • 1 to 32 UDP transmit. and 1 to 32 UDP receive channels 
  • Ethernet Framing processing for non-UDP user-provided packets
  • Optional DHCP client

Trouble-Free Operation

  • Run time programmable network parameters
    • Local MAC address, Local IP address, Gateway IP address, and IP subnet mask
    • Per-channel: Destination IP address, Source and Destination UDP ports, multicast enable/disable and receive group
  • ARP support for operation in networks with Dynamic IP allocation

Easy SoC Integration

  • Flexible interfaces:
    • Packet Data: 64-bit streaming-capable Avalon-ST or AXI4-Stream
    • Control/Status Registers: Generic 32-bit SRAM-like, or optionally 32-bit AHB, AXI, Avalon-MM or Wishbone
  • Separate clock domains for packet processing and control/status interfaces
  • Configurable buffer sizes
  • Rich interrupt support for system events
  • Optionally available pre-integrated with:
    • Intel, Xilinx, or other third-party eMAC cores
    • CAST Image and Video compression cores

 

Resources

Software Tools

  • Wireshark - Open-source packet-analyzer
  • Netcat  - Utility for sending and receiving messages using TCP or UDP.

Related IP Protocols

Ethernet MAC Cores from Intel and Xilinx

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