Building TSN Ethernet networks with CAST IP is now easier with a new multi-port capability on our Switch IP core and recent webinar videos with design tips for achieving ultra-low latency TSN networks.
May 10, 2021
Silicon IP Cores
LIN-VIP
LIN Verification IP
LIN-VIP is a comprehensive VIP package for LIN controllers. SoC and IP designers use this LIN-VIP package to ensure complete verification of their designs and full protocol and timing compliance.
LIN-VIP implements a ready-to-use set of models, protocol checkers, and compliance testsuites in 100% native SystemVerilog and UVM. It supports the latest relevant specifications, including LIN ISO 17987 Part 1-7.
The system configuration uses an LDF class describes complete cluster configuration and information mapping
- Time Base, Jitter
- Participating Nodes & Attributes
- Schedule table
- Collision resolver
- System-wide Signals set (Publishers, Subscribers)
- Frames types (Unconditional, Event, Sporadic, Diagnostic, User-Defined, Wake/Sleep)
- Each node refers to copy of LDF class object for request header and response generation
- Signal and Diagnostic carrying frame class models all frame formats including Header and Response
Support
The LIN-VIP as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first in-teraction. Additional maintenance and support options are available.
Deliverables
The LIN-VIP includes everything required for successful implementation:
- Master and Slave node BFMs
- Compliance Testsuite
- User Guide
Engineered by Avery Design Systems.
Features List
- Supports ISO 17987 Part 1-7
- Backwards compatible
- Master and Slave node BFMs
- Node configuration and identification services
- Automatic frame segmentation and reassembly of network layer messages (FF, CF)
- Automatic frame scheduling to time slot/time base including collision resolution
- Frame transmission ordering and endianness
- Status management that provides error handling and error signaling
- Wake and Go-to-Sleep modes
- Diagnostics
- Response pending
- Diagnostic and Interleaved Diagnostic mode
- Verified with CAST LIN IP
Additional Features
- Timing class models all timing parameters (randomize, modifiable)
- Transport and Network layer timing parameter including time base and jitter
- Multiple bit rates from 1Kbps to 20Kbps
- Inter-frame delay
- Error detection (callback, bit stuffing) and injection
- Random configuration
- Node type, bit timing rate, time base, jitter
- Error injection/Callbacks
- Functional Coverage
- Protocol checking
- Protocol analyzer log
- Compliance testsuite (17987 Part 6)