A family of silicon IP cores for GZIP/ZLIB/Deflate lossless compression and decompression, as well as a LZ4/Snappy decompression core. The IP cores of the family ...
Silicon IP Cores
Featured Products
xSPI, HyperBus™, & Xccela™ Serial Memory Controller
SPI/DSPI/QSPI/OSPI memory controller IP Core compatible with JEDEC’s eXpanded SPI (xSPI), HyperBus™, and Xccela™ standards. Supports Execute-In-Place (XIP) , Access ...
Multiport TSN Ethernet Switch
An ultra-low latency Ethernet switch that supports IEEE 802.1Q bridging and implements the essential Time-Sensitive Networking (TSN) timing synchronization and ...
1G/10G TCP/IP Hardware Stack
An all-hardware TCP/IP stack with speeds up to 10Gbps and extremely low latency. Soft or firm IP core synthesizable to any ASIC or FPGA technology. Soft or firm IP ...
LZ4/Snappy Data Decompressor
High-speed decompression engine for LZ4 and Snappy formats, providing scalable throughput over 100Gbps with error handling and ECC support.
AXI4 to/from AXI4-Stream DMA
AXI4 Memory-Mapped to Stream & Stream to Memory-Mapped DMA. Designed for ease of integration, the AXI4-DMA supports a number of configuration options
PNG Lossless Compression Decoder
An efficient, low-power, lossless compression engine compliant to the PNG file format. Area-efficient, high-performance, and low-latency for ASICs or FPGAs.
SafeSPI Controller
The SafeSPI-CTRL is a flexible and reliable SPI controller compliant with SafeSPI and conventional SPI protocols. It can function as a master, slave, or monitor ...
CAN CC, CAN FD, and CAN XL Bus Controller
ISO-26262 ASIL-D CAN protocol bus controller IP core. Conforms to CAN, CAN FD & CAN XL according to ISO 11898-1:2024; Time-Triggered CAN (TTCAN) per ISO 11898-4; and ...
Latest Updates
Semiconductor intellectual property core provider CAST today announced a new IP core that provides lossless data compression using either the LZ4 or the Snappy ...
Jun 26, 2025
Configurable, streaming-optimized controller efficiently transfers large volumes of data to and from system memory and peripherals over 16 channels in each direction ...
Jun 17, 2025
Certified design IP cores save automotive engineers substantial time and expense in developing Functional Safety conforming ASIC- and FPGA-based systems.
Jun 5, 2025
CAST has developed very flexible licensing terms in collaboration with our customers over the years, resulting in mutually cost-effective solutions. Our competitors can’t come close to discussing licensing with as much understanding as CAST, and it is doubtful that the large IP providers will deviate from their single-project licensing structure at all.
Jun 4, 2025
Among lossless data compression algorithms, GZIP, ZSTD, LZ4, and Snappy have emerged as prominent contenders, each offering unique trade-offs in terms of compression ratio, speed, and resource utilization. This white paper evaluates these algorithms and their corresponding hardware cores, providing an in-depth comparison to help developers and system architects choose the optimal solution for their specific use case.
May 27, 2025
Synchronous and asynchronous ASRC has a broad channel capacity, high conversion ratios, and fast performance, all with outstanding low distortion.
Apr 28, 2025
The CAST DO-254 certified SHDLC HDLC & SDLC Protocol Controller IP Core is an effective solution for replacing obsolete parts in legacy defense and other systems.
Mar 19, 2025
Offers future-proof security to ensure the integrity and confidentiality of communication networks against quantum computer-based attacks
Mar 18, 2025
CAST, a leading provider of silicon intellectual property (IP) solutions, and Shikino High-Tech Co., Ltd., a Japanese company specializing in semiconductor design ...
Mar 12, 2025
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