经验证的质量、低风险、广泛的生态系统和卓越的技术支持使CAST的8051成为许多系统功能的经济高效的解决方案
半导体知识产权提供商CAST今天宣布,杭州晶华微电子股份有限公司——一家领先的模拟混合信号集成电路设计和无晶圆厂半导体供应商——已从CAST获得8051微控制器IP核,用于目前正在开发的一套新芯片。
...The L8051XC1 core implements an MCS®51-compatible microcontroller that is specially designed to match the timing and peripherals of legacy 8051 MCU based systems.
The core can be configured to execute an instruction every 12, 6, or 4 clock cycles. Architectural extensions are user-selectable, including multiple data-pointers, a multiply-division unit, and a power management unit. Furthermore, the 8051 CPU can be coupled with a wide range of peripherals matching the behavior and timing of peripherals found in legacy architectures from various vendors. Several pre-configured versions are offered; custom variations are also available.
The L8051XC1 runs legacy code, but new software development is facilitated through CAST’s on-chip debugging option, and debug pods that cooperate with IAR Embedded Workbench & Keil uVision™ IDEs.
This product builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. Designed for easy reuse in ASICs or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional debug & SPI modules), synchronous reset, and no internal tristates. Representative 40nm ASIC results show the core to be conservative in its use of space, requiring just 7,200 to 40,000 gates.
Three standard versions of the core are available, offering a range of capabilities and prices.
ASIC (RTL) and FPGA (netlist) deliverables are available; FPGA packages are not user-configurable.
The core has been verified through extensive simulation and rigorous code coverage measurements. All subcomponents were functionally verified with an HDL testbench using their individual test suites. The CPU and ALU have been verified against a proprietary hardware modeler and behavioral models. The peripherals have also been verified in their own testbenches, based on either hardware or behavioral models. An extensive constrained random verification was performed to verify the CPU, DMA and OCDS.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available; contact CAST Sales.
The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation. ASIC versions include:
A reference design board is available; contact CAST Sales for information.
L8051XC1 designs have been evaluated in a variety of technologies. The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The target technology is TSMC 40nm. Please contact CAST to get characterization data for your target configuration and technology.
Configuration | Area (Eq. KGates) |
Fmax (MHz) |
L8051XC1-CPU (CPU-only) |
7,231 | 1,210 |
L8051XC1-A (Timer 0 & 1, Serial 0,4 parallel ports) |
10,307 | 1,020 |
L8051XC1-CF (Timer 0, 1 & 2, WDT, RTC, SPI, 2 I2C, Serial 0 & 1, 4 parallel ports, MDU, 8 DPTRs, DPTR Arith., OCDS) |
36,470 | 756 |
The DMA requires an additional 1.5K gates per channel.
The provided figures do not represent the higher speed or smaller area for the core and area figures do not include any memories. Please contact CAST to get characterization data for your target configuration and technology.
Engineered by Silesia Devices.
A wide range of architectural options and peripherals is available for integration with the L8051XC1, and more peripherals can be developed on demand. The following is partial list of the off-the-shelf available peripherals:
Code and debug this 8051 with these popular IDEs:
IAR Systems Embedded Workbench for 8051
These tools work with an optional, native on-chip debug block and inexpensive external adapter (pod) with a JTAG four-wire or SWAT Single-Wire PC interface.
Easily evaluate this 8051's features and performance in your own environment with the
Talos Series Evaluation Kit for 8051s.
Understanding Interrupt Latency in Modern 8051s
by Nikos Zervas at ChipEstimate.com