Silicon IP Cores
Flash, Cache, & SRAM
A set of controller IP cores for different types of memories, including :
- SFLASH-AHB — A universal serial/SPI flash memory controller that allows a system to easily detect and access an attached flash device, or directly boot from it.
- CACHE-CTRL — A flexible cache memory controller providing a 32-bit slave AHB-lite processor interface and a 32-bit master AHB-lite interface to the memory subsystem.
- SRAM-CTRL — An SRAM Controller translating AHB, or AXI4, or APB bus reads and writes into reads and writes with the signaling and timing of a standard 32-bit synchronous SRAM.
- ECC-SRAM — A core that adds Single-Error Correction / Dual Error Detection (SECDEC) to any SRAM, without altering its access latency
Each of these has been production-proven or rigorously verified, and comes with complete deliverables to simplify integration with your system.