Silicon IP Cores
GZIP Lossless Data Compression
Reduce data storage and bandwidth requirements
CAST offers a family of silicon IP cores, reference designs and complete accelerator designs for GZIP/ZLIB/Deflate lossless compression and decompression.
The IP cores of the family are highly configurable to allow fine-tuning of its compression efficiency, throughput, size and latency to match the requirements of the end application. These IP cores have been used to reduce the cost and power for data storage and transfer within SoCs, as well as in big-data servers.
- GZIP, ZLIB, and Deflate compression
- Highly configurable core allows different levels of compression efficiency, throughput, latency and size for different configurations
- Capable of 100Gbps+ & gzip -6 compression level
- Decompression of GZIP, ZLIB, and Deflate files
- Limited versions allow optimizing area and/or latency
- Scalable throughput by multiple core instantiations
Read about them below, see each core's product page, and contact Sales to learn more or discuss how we can support your evaluation.
Complete FPGA accelerator reference designs are available for both Intel and Xilinx boards, including Intel’s PAC and Xilinx’s Alveo boards.
These reference designs are:
- Fast: Capable of throughputs exceeding 80 Gbps.
- Configurable: Throughput, compression efficiency, and size that fit your application requirements.
Compression can be used to significantly reduce the energy consumption related to the power-hungry NVM and RF module of your design:
- NVM: Storing compressed (instead of uncompressed) firmware and decompressing on-the-fly at boot time reduces boot/wake-up energy and time.
- RF: Transmitting compressed (instead of uncompressed data) over your RF link, reduces the active time for your RF front-end, and the energy related to it.
Read more in this white paper: Firmware Compression for Lower Energy and Faster Boot in IoT Devices.