- Capable of running all existing 16450 and 16550a software
- Fully Synchronous design. All inputs and outputs are based on the rising edge of clock
- In FIFO mode, transmitter and receiver are each buffered with up to 256 byte FIFO’s to reduce the number of interrupts presented to the CPU
- Available with FIFO sizes of 8, 16, 32, 64, 128 or 256 bytes
- Adds or strips standard asynchronous communication bits (start, stop and parity) to or from the serial data
- Independently controlled transmit, receive, line status and data set interrupts
- Programmable baud generator divides any input clock by 1 to (2**16 - 1) and generates the 16 x clock
- Modem control functions (CTSn, RTSn, DSRn, DTRn, and DCDn)
- Programmable Auto-CTSn and Auto-RTSn
- In Auto-CTSn mode, CTSn controls the transmitter
- In Auto-RTSn mode, the receiver FIFO contents and threshold control RTSn
- Serial Port has an optional Infrared Data Association (IrDA) data port
- Fully programmable serial interface characteristics:
- 5, 6, 7, or 8 bit characters
- Even, odd, or no-parity bit generation and detection
- 1, 1½, or 2 stop bit generation
- Baud generation
- False start-bit detection
- Complete status register
- Internal diagnostic capabilities: loop-back controls for communications link fault isolation
- Full prioritized interrupt system controls
UART IP Core H16750S Synchronous 16750 UART with FIFO & IrDA Core
The H16750S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16750 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices.
The H16750S can be run in either 16450-compatible character mode or FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead. An IrDA-compliant serial data port may be used for infrared communication.
Developed for easy reuse in ASIC and FPGA applications, the H16750S is available optimized for several device families with competitive utilization and performance characteristics.
See representative implementation results (each in a new pop-up window):
Applications
The H16750S can be utilized for a variety of applications including:
- Serial or modem computer interface
- Serial interface within modems and other devices
Symbol Diagram
Block Diagram
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Wrapper for pin compatible replacement
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
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