Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

SENT/SAE J2716 Receiver & Transmitter

  • Fast and Slow Channel Transmit or Receive
  • CRC generation for Transmitter, and CRC checking for Receiver
  • All types of SENT Frames
    • Programmable data length (4 to 24 bits) for Fast Channel Frames
    • Short (8-bit data) and Enhanced (12- or 16-bit data) Message Formats for Slow Channel
  • Optional Pause Pulse with programmable length
  • Supports inverted SENT protocol

Short PWM Code (SPC) Receiver & Transmitter

  • Allows up to four sensors (transmitters) to use the same physical SENT connection
  • Programmable master trigger pulse length

Ease of Integration

  • 32-bit APB interface, and comprehensive set of interrupts
  • Programmable 4-bit clock divider and high precision 16-bit clock pre-scale
  • Receive and Transmit FIFO of configurable size for Fast Channel data
  • Run-time programmable configuration registers
  • Synthesis-time defined reset values for all registers, enables data transmit without control from host processor
  • LINT-clean, single-clock domain, scan-ready design

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

News Releases

CSENTSENT/SAE J2716 Controller Core

The CSENT core implements a controller for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and also the industry de-facto standard Short PWM Code (SPC) protocol, and can be used for conveying data from one or multiple sensors to a centralized controller using a single SENT line.

CSENT is part of the line of automotive IP cores from CAST, Inc.The CSENT core can be configured as a Transmitter and/or as a Receiver, and therefore it is suitable for adding a SENT interface to devices transmitting sensor data or to controllers receiving sensor data. It provides access to its control, status, and data registers via a 32-bit APB bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation. The core allows for Transmitter operation without requiring any external programming or control. The reset values for all its control registers are defined at synthesis time, and at run time the system only needs to write sensor data to the core.

The CSENT core is designed with industry best practices. The core contains no latches or tri-sates, and is fully synchronous with a single clock domain. The core is available in Verilog RTL or as targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.

See representative implementation results (each in a new pop-up window):

PCIe core ASIC numbers Altera numbers Xilinx numbers

Applications

The CSENT core is suitable for designing low-cost digital automotive sensors, and automotive controller units.

Block Diagram

CSENT block diagram

Deliverables

The core includes everything required for successful implementation:

 

tw    fbk    li    li    li
Top of Page