Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Flexible SPI Master/Slave

  • Software programmable Master or Slave mode
  • Software programmable SCLK rate
  • 8-bit, 16-bit, 24-bit, and 32-bit synchronous serial transmission
  • Full duplex operation
  • 16 word/byte Transmit FIFO (configuration option)
  • 16 word/byte Receive FIFO (configuration option)
  • AMBA APB interface
  • Interrupt control
  • LSB or MSB mode
  • Up to four slaves under Master control
  • Tristate Slave MISO signaling for multiple slaves

 Smooth Technology Mapping

  • Fully synchronous, scan-ready, design architecture

Delivered with sample scripts, RTL test-bench and sample test-cases

 

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

  • OSPI-XIP-AHB Single, Dual, Quad, & Octal SPI Flash Controller for AHB
  • QSPI-XIP-AHB Quad SPI Bus Controller with XIP, for AHB
  • QSPI-XIP-AXI Quad SPI Bus Controller with XIP, for AXI
  • QSPI-APB Quad-Bit Serial Peripheral Interface Master/Slave
  • SPI2AHB SPI to AHB-Lite Bridge

More Information

SPI-APB Master/Slave Serial Peripheral Interface Bus Controller

Implements a synchronous serial data link controller that functions as either a master or a slave device over the standard Serial Peripheral Interface (SPI) Bus,

SPI Bus IP cores icon at CAST Inc.The SPI-APB bus controller can be configured under software control to be a master or slave device. Reading and writing the core is done via the AMBA® APB bus interface. The core operates in 8-bit, 16-bit, 24-bit, and 32-bit data modes. The data is then serialized and transmitted from master to slave device using the standard four-wire SPI bus interface.

The data is transmitted synchronously with the MOSI (Master Out, Slave In) relative to the SCLK generated by the master device. The master also receives data on the MISO (Master In, Slave Out) signal in a full duplex fashion.

The SPI-APB controller can be used with up to four slave devices. When the core is configured as a slave, the MISO signal is tristated to allow for multiple slaves to transmit data to the master when the slave is selected.

The SPI-APB core is proven and available in RTL source or as a targeted FPGA netlist.

Applications

The SPI-APB core is suitable for implementing serial interfaces in a wide range of applications, including host communication with flash memories, and peripherals such as sensors, ADC/DACs, touchscreens, video game controllers, and audio/video codecs.

Block Diagram

spi-apb block diagram

Support

The SPI-APB as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical sup-port are included, starting with the first interaction. Additional maintenance and support options are available.

 

Comparing SPI Cores Family

Core Name
Features
SPI Mode
SPI
Master
SPI
Slave
DTR
XIP
DMA IF
Host
Interface

SPI-APB

1x
supported
supported
not supported
not supported
not supported
APB
QSPI-APB
1x, 2x, 4x
supported
supported
not supported
not supported
supported
APB
QSPI-XIP-AHB
1x, 2x, 4x
supported
supported
not supported
supported, but may be removed
supported
AHB
QSPI-XIP-AXI
1x, 2x, 4x
supported
supported
not supported
supported, but may be removed
supported
AXI
OSPI-XIP-AHB
1x, 2x, 4x, 8x
supported
not supported
supported
supported, but may be removed
supported
AHB

     supported, but may be removed Feature supported, but can optionally be removed
     supported Feature supported
     not supported Feature not supported
     DTR: Dual Transfer Rate
     XIP: Execute in place

 

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