- I2C Slave Transmit and Slave Receive Modes
- I2C Bus Speeds
- Standard-mode (Sm): up to 100 Kbps
- Fast-mode (Fm): up to 400 Kbps
- Fast-mode Plus (Fm+): up to 1Mbps
- High-Speed mode (Hs): up to 3.4 Mbps
- Unidirectional Ultra Fast Speed (UFm): up to 5 Mbps
- Programmable 7 bits slave address
Easy to Use
- Control and monitor via 8-bit-wide control status registers
- Maskable interrupts
- Read and write data FIFOs
- Separate clocks for bus interface and I2C bus sampling
- Low Level Driver in C
- Host Interface options include, APB (default), AHB, Wishbone, and 8051-SFR
Call or click.
- SPMI-CTRL MIPI SPMI Master or Slave Controller
- I2C-M I2C Bus Master Controller Core
- I2C-SMBUS I2C & SMBus Controller Core
I2C-SI2C Bus Slave Controller Core
Implements an Inter-Integrated Circuit (I2C) Bus slave controller that meets the Phillips I2C version 1.4 specification.
Under its default configuration, the I2C-S provides access to its 8-bit-wide status and control registers via an APB-slave port. Alternatively, the core can be equipped with an AHB-slave, Wishbone-slave or generic microcontroller interface.
The I2C-S allows dynamic control of the serial clock frequency, and the I2C bus speed is only limited by the external bus driver capabilities. The I2C slave 7-bit address is programmable, and the core uses FIFOs for transmit and receive data to reduce the host overhead. Being accompanied by a low-level C-driver, the I2C-S core enables easy and rapid development of over-I2C, or I2C-like protocols in user applications.
The I2C-S is production proven in ASIC and FPGA technologies.
The I2C-S enables adding I2C slave interface to microcontrollers or peripheral devices, such as A/D and D/A Converters, sensors, smart cards, and radio or video systems.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core is available in Verilog RTL or as a targeted FPGA netlist. Its deliverables include everything required for a successful implementation, including an extensive testbench, comprehensive documentation and a low-level device driver.