Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

  • I2C Slave Transmit and Slave Receive Modes
  • I2C Bus Speeds
    • Standard-mode (Sm): up to 100 Kbps
    • Fast-mode (Fm): up to 400 Kbps
    • Fast-mode Plus (Fm+): up to 1Mbps
    • High-Speed mode (Hs): up to 3.4 Mbps
    • Unidirectional Ultra Fast Speed (UFm): up to 5 Mbps
  • Programmable 7 bits slave address

Easy to Use

  • Control and monitor via 8-bit-wide control status registers
  • Maskable interrupts
  • Read and write data FIFOs
  • Separate clocks for bus interface and I2C bus sampling
  • Low Level Driver in C

Configurable

  • Host Interface options include, APB (default), AHB, Wishbone, and 8051-SFR

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

  • SPMI-CTRL MIPI SPMI Master or Slave Controller
  • I2C-M I2C Bus Master Controller Core
  • I2C-SMBUS I2C & SMBus Controller Core

Additional Information

I2C-SI2C Bus Slave Controller Core

Implements an Inter-Integrated Circuit (I2C) Bus slave controller that meets the Phillips I2C version 1.4 specification.

Under its default configuration, the I2C-S provides access to its 8-bit-wide status and control registers via an APB-slave port. Alternatively, the core can be equipped with an AHB-slave, Wishbone-slave or generic microcontroller interface.

The I2C-S allows dynamic control of the serial clock frequency, and the I2C bus speed is only limited by the external bus driver capabilities. The I2C slave 7-bit address is programmable, and the core uses FIFOs for transmit and receive data to reduce the host overhead.  Being accompanied by a low-level C-driver, the I2C-S core enables easy and rapid development of over-I2C, or I2C-like protocols in user applications.

The I2C-S is production proven in ASIC and FPGA technologies.

Block Diagram

I2C Bus Slave Controller Block Diagram

Applications

The I2C-S enables adding I2C slave interface to microcontrollers or peripheral devices, such as A/D and D/A Converters, sensors, smart cards, and radio or video systems.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in Verilog RTL or as a targeted FPGA netlist. Its deliverables include everything required for a successful implementation, including an extensive testbench, comprehensive documentation and a low-level device driver.

 

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