Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

  • I2C Master Transmit and   Master Receive Modes, suitable for uni-master buses
  • I2C Bus Speeds
    • Standard-mode (Sm): up to 100 Kbps
    • Fast-mode (Fm): up to 400 Kbps
    • Fast-mode Plus (Fm+): up to 1Mbps
    • High-Speed mode (Hs): up to 3.4 Mbps
    • Unidirectional Ultra Fast Speed (UFm): up to 5 Mbps
  • 7- and 10-bit slave address
  • Acknowledge/Not Acknowledge cycle by slave (required for all modes but UFm) or master (required by UFm)
  • Clock Stretching Support
  • Suitable for implementing I2C variants such as SMBUS and PMBUS

Easy to Use

  • Control and monitor via 8-bit-wide control status registers
  • Compact set of commands control I2C Transactions
  • Rich set of maskable interrupts
  • Command and read FIFOs for lower host overhead
  • Programmable clock divider derives serial clock from bus clock or externally provided clock
  • Low-Level Driver in C

Configurable

  • Host Interface options include APB (default), AHB, Wishbone, and 8051-SFR
  • Adjustable Receive Data and Command FIFO sizes

Contact Sales
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Downloads (PDFs)

Related Products

  • I2C-S I2C Bus Slave Controller Core
  • I2C-SMBUS I2C & SMBus Controller Core

Addditional Information

I2C-MI2C Bus Master Controller Core

Implements an Inter-Integrated Circuit (I2C) Bus master controller that meets the Phillips I2C, version 4.0 specification for single master I2C buses.

i2c-m block diagram

The I2C-M allows dynamic control of the serial clock frequency, and the I2C bus speed is only limited by the external bus driver capabilities and the frequency used to clock the core. It supports a 7- or 10-bit slave address and allows the Acknowledge cycle to be controlled by either the slave or the master. This enables operation in all bus speed modes provisioned by version 4.0 of the standard, including the unidirectional Ultra Fast Speed. Furthermore, the core is suitable for implementing the master node for I2C-based protocols, such as SMBUS, PMBUS and VESA Display Data Channel (DDC).

Under its default configuration, the I2C-M provides access to its 8-bit-wide status and control registers via an APB-slave port. Alternatively, the core can be equipped with an AHB-slave, Wishbone-slave, or generic microcontroller interface.

Controlled by a compact and comprehensive set of commands and accompanied by a low-level C-driver, the I2C-M core enables easy and rapid development of over-I2C, or I2C-like protocols in user applications. The configurable size FIFOs for read-data and commands and a rich set of interrupts help reduce host processor overhead and interaction.

The I2C-M is production-proven in ASIC and FPGA technologies.

Applications

The I2C-M enables microcontrollers to interface I2C peripherals such as EEPROM, A/D and D/A Converters, sensors, smart cards, and LCD and LED drivers.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in Verilog RTL or as targeted FPGA netlist, and its deliverables include everything required for a successful implementation, including an extensive testbench, comprehensive documentation and a low-level device driver.

 

 

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