IP Subsystem R8051XC-HDLC HDLC Connectivity Platform

On this page: Description | Features | Applications | Block Diagram | Functional Description | Performance | Verification | Configurability | Support | Deliverables

The HDLC Connectivity Platform  integrates the R8051XC 8-bit microcontroller with the HDLC Protocol Controller.

The main purpose of the HDLC Connectivity Platform is to ease the building of an 8051-based HDLC microcontroller and to offer a ready-to-use reference design for development of both a complete HDLC protocol, and derivative-based solutions.

The HDLC Connectivity Platform features an HDLC serial interface. The HDLC portion of the solution provides needed serialization and de-serialization. It also supports automatic response generation for window size equal to 1.

The HDLC Connectivity Platform retains features of the R8051XC configurable 8-bit microcontroller. It provides interrupts, interfaces for serial communication, timer system with compare-capture-reload resources, I/O ports, a power management unit, a multiplication-division unit, DMA controller, watchdog timer, and a real time clock. The extensive set of peripherals included can be easily modified to meet the requirements of a specific application.

The HDLC Connectivity Platform is a design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset; therefore scan insertion is straightforward.

Features

R8051XC 8-bit µcontroller

• Fast single clock per cycle CPU
• Flexible interfaces to program and data memories
• Extensive set of optional and configurable peripherals
• On-chip Debug Support unit (optional)
• External memory interface
• Multiplication-Division Unit
• Special Function Registers interface
• Interrupt Controller
• Power Management Unit
• DMA Controller
• 16 Bit Timers/Counters
• SPI Master/Slave interface
• One or two I2C™ Master/Slave interfaces

HDLC Protocol Controller

• Two independent HDLC channels
• LAPB/LAPD controlling machine
• Serial Peripheral Interfaces
• Receive Length Check
• Three modes of receive operation
• Receive and transmit blocks
• Separate FIFOs

Applications

• X.25 link control
• ISDN applications
• General purpose telecommunication applications

Block Diagram

Functional Description

The core is made up of several functional blocks, as shown in the block diagram and described below.

R8051XC-CPU

This unit contains instruction execution FSM along with dedicated registers, such as Program Counter, Stack Pointer and Data Pointer(s). The Arithmetic-Logic Unit is also implemented in this module, together with the following registers: Accumulator, B and Program Status Word. Moreover, the CPU module provides and services interfaces to program and external data memory, on-chip data memory, and Special Function Registers.

Feature summary of the R8051XC-CPU:

• 8-bit Control Unit reducing instruction cycle time up to 12 times
• 8-bit Arithmetic-Logic Unit executing arithmetic and logical operations, Boolean manipulations, multiplication and division
• Internal Data Memory interface addressing up to 256 B of Data Memory Space
• Special Function Registers (SFR) interface -  servicing  from 59 to 118 SFR’s, depending on the peripheral configuration
• External memory interface allowing easy connection to memories via de-multiplexed Address/Data Bus, implementing variable length accesses to work with fast/slow peripherals, data, and program memories. It utilizes up to 8 Data Pointers for fast data block transfers. It also supports an external DMA controller through the HOLD interface.
• Memory banking supporting up to 8 MB of both program and data memory space
• Program memory write mode
• Internal DMA controller with up to 8 software configurable channels
• On-chip Debug Support interface to JTAG port

HDLC

The HDLC Protocol Controller functionality is similar to Siemens HSCX, and provides serial interface for connecting SDLC/HDLC based systems.

Feature summary of HDLC Protocol Controller:

• Internal timer
• HDLC protocol engine
• 64B FIFO in transmit direction
• 64B FIFO in receive direction
• 16B FIFO to provide multiple frame storage in receive direction
• Special Function Registers section for configuration
• Engine for automatic address and control field insertion
• Transfer engines for interrupt and DMA transfers
• RTS/CTS flow control
• CD sense for enabling/disabling receiver
• Collision detection in bus mode
• Bus IDLE state detection
• Four different clock modes

MEMMUX

This unit works as a multiplexer, enabling CPU communication with both external data memory and HDLC Protocol Controller.

It contains a configurable address decoder for the HDLC Protocol Controller, and can be placed in an address space from 0000H up to 0FFFFH.

R8051XC-OCDS

The OCDS unit serves as interface for the On-Chip Debug Support through an IEEE1149.1 (JTAG) port. The OCDS unit provides the following functions:

• Run/stop control
• Single-step mode
• Software breakpoints
• Debugger program execution
• Hardware breakpoints
• Read/Write Access to Program Memory, External/Internal Data Memory, and SFR’s
• Program Trace (optional)
• Data Trace (optional)

R8051XC-PER

This block is a set of other permanent or optional R8051XC components and peripherals:

• Up to four 8-bit Input/Output ports
• Up to three 16-bit Timer/Counters
• Four 16-bit Compare/Capture registers for Pulse with Modulation, Pulse with Measuring, or for Pulse Generation
  
• Up to two Full Duplex Serial Interfaces, working in Synchronous mode and fixed baud rate, or 8-bit/9-bit UART mode and variable/fixed baud rate
• 32/16-bit Multiplication-Division Unit
• 15 bit Programmable Watchdog Timer
• Real Time Clock
• Power Management Unit, providing two power reduction modes: IDLE and STOP
• Up to two I2C™ interfaces
• SPI interface

R8051XC-ISR

The Interrupt Service Routine unit services up to 18 interrupt sources (besides the HDLC interrupt) at four priority levels.

The HDLC interrupt is connected to the R8051XC interrupt logic directly – it does not reduce the external interrupt inputs available to the user.

R8051XC-DMA

The Direct Memory Access unit provides up to 8 configurable channels with two priority levels. Each channel can be configured independently. The DMA unit services up to 18 interrupts (besides the HDLC interrupt) as transfer triggers. Each channel can act as an interrupt source to indicate the end of a transfer. These interrupts are shared with external interrupts.

The HDLC DMA request signals are connected to DMA logic directly and do not reduce the external interrupt inputs available to the user.

Performance

The HDLC Connectivity Platform targets designers looking for a powerful 8-bit microcontroller integrated with an HDLC protocol controller.

The architecture eliminates redundant bus states and implements parallel processing of fetch and execution phases. Since a CPU cycle is aligned with memory fetch when possible, most of the 1-byte instructions are performed in a single cycle. The R8051XC uses 1 clock per cycle. This, together with other extensions (mutli-DPTR, MDU), leads to performance improvement at the rate of 9.6 (in terms of DMIPS), with respect to the Intel device working with the same clock frequency.

Verification Methods

The HDLC Connectivity Platform has been verified through extensive functional simulation and prototyped in an FPGA-based application.

The functional verification of subcomponents was performed in an HDL testbench. All subcomponents of R8051XC were verified together in the same testbench environment, even though the most important ones have individual test suites.  The R8051XC-CPU with an arithmetic-logic unit was verified against behavioral models, as well as a hardware model developed with a proprietary hardware modeler.

The peripherals, including the HDLC Protocol Controller IP core, have also been verified in their own testbenches, based either on hardware or behavioral models.

Configurability

The following parameters allow adjustment of the HDLC Connectivity Platform core to the requirements of target applications:

• Configurable base address for HDLC address space: from 0000H up to 0FF00H
• R8051XC configurability
• Size of external data/program memory: 64kB - 8MB
• Number of DPTR registers: 1, 2 or 8
• Number of  8-bit I/O ports: 0 ... 4
• Number of 16-bit timers: 0 … 3
• Number or serial ports: 0, 1 or 2
• Watchdog timer: 0 or 1
• Multiplication-Division unit: 0 or 1
• I2C master-slave interface: 0, 1 or 2
• SPI master-slave interface: 0 or 1
• On-chip debug support: OCI or OCDS
• Rarely used instructions MUL, DIV, DA: yes or no
• Support for external DMA operations: yes or no
• Number of DMA channels: 0 ... 8

A user-friendly tool with a Graphical User Interface is provided for smooth configuration.

Support

The platform as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core includes everything required for successful implementation. The ASIC version includes:

• HDL RTL source code
• An example chip design
• Integrates the R8051XC with HDLC
• Illustrates how to build and connect interrupt signals, memories and port modules
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) that instantiates example design, external RAM, clock generator, program memory model with random code generation mode, and monitors that compare simulation results with expected results
  
• A collection of 8051 assembler programs that are executed directly the Test Bench
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Features | Applications | Block Diagram | Functional Description | Performance | Verification | Configurability | Support | Deliverables

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