Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

More Info

What's Your Bright Idea?
Watch this video by our Subsystem's lead archtiect.


Take Five with Warren Savage and Jim Bruister

Jim explains the technical approach and advantages of these IP Subsystems.

News Releases

IP SubsystemsPre-Integrated and Verified Processor-Based Systems

The IP Subystems available from CAST provide the quickest path from your creative product idea to a competive working system.

These register transfer level Subsystems are designed with the total system in mind. They combine an AMBA™ bus infrastructure with typical peripheral, interface, and memory controller IP cores and all essential drivers and software, all in a verification environment that emulates the software and hardware together, at a system level.

Drop in your choice of processor core and memory devices, develop your application software, test the working system, and you're ready to produce an FPGA or ASIC with little risk in a remarkably short time.

Rapid System Development and Test

Our Verilog/SystemVerilog based verification environments make it easy to use with any of the standard simulation tools from Cadence, Mentor Graphics or Synopsys. All of our peripherals, DMAs, buses and memory controllers are delivered with comprehensive stand-alone tests using AMBA® standard transaction or Bus Functional Models (BFM).

Straightforward Customization

The Subsystems are designed for easy customization, whether before delivery with additional APB cores or instances or after delivery in your own system design. The Power Management Unit, for example, is designed as two asynchronous power sequencing state-machines, so that the exact power sequences can be customized to best fit your application’s power needs.

Complete Deliverables

The Subsystems are delivered as Verilog Source, and include everything required for successful implementation.

A complete subsystem-level test environment that is easily adaptable for additional integration is included. An AMBA® 2.0 Bus Functional Model is included for simulation and verification, as are sample C drivers and test code.

Integration and Verification Services

The engineers who developed the AHB-LP Subsystem can provide integration and verification services to help you further reduce your time to market. Extremely experienced with both system hardware and custom software development, they are ready to work with you at any stage of the design process from architecture to implementation to system level verification to produc-tion readiness. Contact CAST Sales to learn more.

Features

Supports BA22-DE, BA22-CE, or ARM Cortex-M0 class processors

Includes:

  • Power Management Unit
  • AMBA® 3.0 AHBLite/APB bus infrastructure
  • AHB/APB bridge
  • Internal SRAM and Flash Memory controllers
  • Interrupt Controller (optional)
  • Standard APB Peripheral package
    • I2C, SPI, UART, GPIO
    • Timer, Watchdog Timer

AHB-LP Low-Power AHB Subsystem

Provides an integrated, verified, AMBA® 3.0 compliant hardware/software system ready for deploying ultra-low-power applications using processors such as the BA22-DE, BA22-CE, or ARM Cortex-M0.

The AHB Low Power Subsystem combines peripheral and interface IP cores with drivers and other essential software and an AHBLite/APB bus infrastructure. It is designed to work well with the user’s choice of low-power processor, and has been specifically tested with those from CAST and ARM.

The subsystem includes a package of standard APB peripherals: I2C, SPI, UART, and GPIO interfaces, plus a Timer and Watchdog Timer. An AHB-APB Bridge interfaces these with the AHB bus, on which resides included SSRAM and Flash Memory Controllers, the user’s processor core, and any additional CAST or third-party IP cores desired. An Interrupt Controller is also available.

All the included cores are supported with C code drivers and comprehensive tests.

An integrated Power Management System provides an effective means to minimize power consumption for each specific application.

Applications for which this subsystem is designed include battery- or energy-harvesting-powered IoT and M2M devices where minimal energy consumption is a priority over computing capability. Examples are water meter sensors, automobile sensors, and implantable medical devices

Features

Supports BA22-DE, BA22-CE, or ARM Cortex-M0 class processors

Includes:

  • Power Management Unit
  • AMBA® 3.0 AHBLite/APB bus infrastructure
  • AHB/APB bridge
  • Internal SRAM and Flash Memory controllers
  • Interrupt Controller (optional)
  • Standard APB Peripheral package
    • I2C, SPI, UART, GPIO
    • Timer, Watchdog Timer

AHB-PLP Performance/Low-Power AHB Subsystem

Provides an integrated, verified, AMBA® 3.0 compliant hardware/software system ready for deploying ultra-low-power applications using processors such as the BA22-DE, BA22-CE, or ARM Cortex-M0.

The AHB Low Power Subsystem combines peripheral and interface IP cores with drivers and other essential software and an AHBLite/APB bus infrastructure. It is designed to work well with the user’s choice of low-power processor, and has been specifically tested with those from CAST and ARM.

The subsystem includes a package of standard APB peripherals: I2C, SPI, UART, and GPIO interfaces, plus a Timer and Watchdog Timer. An AHB-APB Bridge interfaces these with the AHB bus, on which resides included SSRAM and Flash Memory Controllers, the user’s processor core, and any additional CAST or third-party IP cores desired. An Interrupt Controller is also available.

All the included cores are supported with C code drivers and comprehensive tests.

An integrated Power Management System provides an effective means to minimize power consumption for each specific application.

Applications for which this subsystem is designed include battery- or energy-harvesting-powered IoT and M2M devices where minimal energy consumption is a priority over computing capability. Examples are water meter sensors, automobile sensors, and implantable medical devices

Features

Supports all BA2x Processors, ARM Cortex A5 class processors, or any processor with an AMBA® 4.0 AXI bus interface

Includes:

  • AMBA® 4.0 AXI Multi-layer bus infrastructure
  • AXI/APB bridge
  • Power Management Unit
  • DMA (single or multi-channel)
  • Internal SRAM Controller
  • External NOR Flash Memory Controller
  • DDR2/3 Support (via third-party IP)
  • Interrupt Controller (optional)
  • Quad SPI with Execute in Place (XIP) interfaces with efficent Flash parts from WInbond and Spansion
  • Standard APB Peripheral package:
    • I2C, SPI, UART, GPIO
    • Timer, Watchdog Timer

AXI-CP Custom Performance AXI Subsystem

Provides an integrated, verified, AMBA® 4.0 compliant, AXI Multi-layer bus hardware/software system ready for deploying complex applications using processors such as the BA2x line or ARM Cortex-A5 class processors.

With a suitable processor and memory devices, this subsystem is ready for applications that target complex devices needing both higher performance and perhaps multiprocessing. The subsystem can perform digtial signal procssing, spectral analysis, or complex system control along with moving data efficiently using multiple DMA channels. It also handles complex system-level communications while supporting advanced operating systems such as Android or Linux.

Functional Description

The Custom Perfromance AXI Subsystem combines peripheral and interface IP cores with drivers and other essential software and an AXI multi-layer bus infrastructure. It is designed to work well with the user’s choice of AMBA® 4.0 AXI compliant processor, and has been specifically tested with those from CAST and ARM.

An ingegrated QSPI core allows the subsystem to boot efficiently using standard external QSPI Flash memory from companies such as Winbond and Spansion. The QSPI Execute in Place (XIP) feature allows the subsystem to use smaller on-chip SRAM with the processor fetching instructions directly from off-chip Flash memory (especially efficient when using L1 or L2 cache).

The subsystem includes a package of standard APB peripherals: I2C, SPI, UART, and GPIO interfaces, plus a Timer and Watchdog Timer. An AHB-APB Bridge interfaces these with the AHB bus, on which resides included SSRAM and Flash Memory Controllers, the user’s processor core, and any additional CAST or third-party IP cores desired. An Interrupt Controller is also available.

All the included cores are supported with C code drivers and comprehensive tests.

An integrated Power Management System provides an effective means to minimize power consumption for each specific application.
 

Peripheral IP Cores

These standard CAST cores are available for integration with any Subsystem:

These additional cores are available by special order (contact CAST Sales for details):

  • AHB to APB Bridge
  • AHB Arbiter
  • AHB Channel with Decoder and Data-Mux
  • AHB Lite to AHB Bridge
  • APB Channel with Decoder and Data-Mux
  • APB General Purpose I/O with Interrupt
  • APB Interrupt Controller
  • APB Pulse Width Demodulator
  • APB Real Time Clock APB Timer
  • APB Watchdog Timer
  • Semi-custom Power Management Unit

 

Peripherals

Processor Subsystems include the most typical peripherals, and adding more as needed is easy.

Four powerful infrstructure time savers follow; also see the additional Peripherals avaailable to the right.

AHB Multilayer Fabric IP Core

The AHB Fabric provides the necessary infrastructure to connect as many as seven shared AHB Slaves (numbered 1-7) to as many as three AHB-Lite Bus Masters.

In a typical AHB system, several AHB Masters may compete for a shared (AHB) bus; a bus arbiter determines bus ownership. The AHB Fabric allows for the various AHB-Lite Masters to connect to several different shared peripherals without the need to arbitrate for a shared AHB bus. Instead, arbitration is performed at the peripheral.

This way, the various Masters may see a significant increase in performance over a standard AHB system. However, systems where multiple masters need frequent access to the SAME peripheral will see only a modest performance increase.

The AHB Fabric may be used as either a partial or a complete AHB-Lite subsystem. That is, it may be used in a standalone fashion to comprise a complete AHB subsystem, or in conjunction with an AHB Channel module as part of a larger AHB subsystem.

If used in conjunction with an AHB Channel, because both the Fabric and the Channel perform address decoding, it is important that the decoded address space for the Fabric be mutually exclusive to that of the AHB Channel.

The Fabric may be connected to the remainder of the subsystem as follows.

  • Each of the AHB Fabric’s seven Mirrored Slave Ports is connected to an AHB Slave module (e.g. External Bus Interface, Memory Controller, AHB-to-APB Bridge).
  • On the Master side, each of the three AHB Fabric’s Mirrored Master Ports is connected to either the output side of an AHB Arbiter (in the case where each AHB system has multiple bus Masters) or directly to an AHB or AHB-Lite Master such as a microprocessor.
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AXI Multi-Layer Interconnect IP Core

The AXI Interconnect provides the necessary infrastructure to connect as many as eight shared AXI Slaves to as many as four AXI Bus Masters.

AXI defines five channels (write address, read address, write data, read data, and write response) for its interface signaling between the AXI Master and AXI Slave, but does not define a single way that an AXI Master must be connected to an AXI Slave.

In general, an interconnect module is necessary when more than one Master and/or more than one Slave is required.

The AXI Interconnect is responsible for:

  • routing a transaction from a given Master to the appropriate Slave (decoding and switching), and
  • ensuring that the various Master transactions do not interfere with each other (arbitration).

This AXI Interconnect allows for the various AXI Masters to connect to several different shared peripherals without the need to arbitrate for shared channels. Instead, each Master has its own private connection to each Slave; arbitration for the Slave’s resources is performed at the Slave. This way, the various Masters may see a significant increase in performance over an AXI Interconnect in which several AXI Masters compete for shared channels.

The AXI Interconnect may be used as either a partial or a complete AXI subsystem. That is, it may be used in a standalone fashion to comprise a complete AXI subsystem, or in conjunction with other AXI Interconnects of varying capability as part of a larger AXI subsystem.

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AXI - APB Bridge IP Core

The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one governing the AXI transactions, and one governing APB transactions.

The AXI to APB Bridge acts as an AXI Slave, and an APB Master in an AXI/APB subsystem. Typically, the AXI to APB Bridge has its AXI interface connected to a Slave port on an AXI Channel/Interconnect module, and its APB interface connected to the Master port on an APB Channel module.

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AXI - AHB Lite Bridge IP Core

The AXI to AHB Lite Bridge translates an AXI bus transaction (read or write) to an AHB Lite bus transaction. It is expected that the AXI clock and the AHB clock are derived from the same clock source, and that the period of the AHB Lite clock is an integer multiple of the AXI clock in the range [1,16].

Logic on two synchronous clock domains is used to accomplish the translation.

The AXI logic is responsible for responding to transaction requests from the AXI master, for buffering transaction information to be used by the AHB Lite logic, and for presenting data from the AHB Lite logic back to the AXI master.

The AHB Lite logic is responsible for generating AHB Lite transactions based on transaction information from the AXI logic, and for presenting data from the AHB Lite subsystem back to the AXI logic.

The AXI to AHB Lite Bridge acts as an AXI Slave, and an AHB Lite Master in an AXI/AHB subsystem. Typically, the AXI to AHB Lite Bridge has its AXI interface connected to a Slave port on an AXI Channel/Interconnect module, and its AHB Lite interface connected to the Master port on an AHB Channel module.

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