PDF datasheets:
ASIC (R8051XC-CUSB)
ASIC (R8051XC-CUSB2)
Related information:
03/07/08 CAST Expands Platform IP Offerings with Embedded Internet and USB Subsystems
IP Subsystem R8051XC-CUSB2 Embedded USB Subsystem
On this page: Description | Block Diagram | Example Application | Support | Verification | Deliverables
The R8051XC-CUSB(2) subsystem combines an 8-bit processor core, a USB full- or hi-speed device controller core, and a USB software stack to provide Internet connectivity for System on Chip (SoC) designs.
The subsystem pre-integrates these cores:
Block DIagram
Example Application
This subsystem example application works as a USB Mass Storage system. It transmits data between the hard disk drive and the PC using the subsystem’s USB connection. The CPU controls the settings of endpoints and services interrupts. The main data transfer is performed by the 8051 CPU and DMA to and from the hard disk by means of an ATAIF controller (a separately available CAST core).
Note that some elements in such an example application are technology or design dependent, and must be added on their own. These elements include:
- USB PHY – the subsystem works with industry-standard PHYs,
- Endpoint Memory – a synchronous single port RAM block, and
- Processor Data & Program Memory – dedicated memory blocks for data and program.
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
All subcomponents were functionally verified with an HDL testbench using their individual test suites. The CPU and ALU have been verified against a proprietary hardware modeler and behavioral models. The peripherals have also been verified in their own testbenches, based on either hardware or behavioral models.
Deliverables
The core includes everything required for successful implementation:
- Verilog RTL source code (EDIF netlist available)
- An example chip implementation, which uses the subsystem in a sample system
- Sophisticated Verilog Testbench (Verilog 2001)
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
On this page: Description | Block Diagram | Example Application | Support | Verification | Deliverables
Download PDF datasheets for more info: ASIC (R8051XC-CUSB) | ASIC (R8051XC-CUSB2)
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