Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit the product page:

  • LLEMAC-1G Low-Latency 10/100/1000 Ethernet MAC

News Low-Latency Ethernet MAC IP Core from CAST now ASIL-D Certified

ASIC and FPGA IP core is ready to reduce development time and risk for automotive system designers using Time Sensitive Networking (TSN) Ethernet

Automotive Ethernet Congress, Munich, Germany, February 11 2020

Semiconductor intellectual property (IP) provider CAST, Inc. today announced that the Low-Latency Ethernet Media Access Controller IP core it offers is now certified to conform to the ISO-26262 safety standard and is available ASIL-D ready.

Low-Latency ASIL-D eMAC IP Core Block DiagramThe LLEMAC-1G Low-Latency 10/100/1000 Ethernet MAC core features extremely low input and output latencies, making it ideal for TSN Ethernet nodes, live video streaming, and other systems requiring minimum delays in the reception and transmission of Ethernet frames. The company believes it is the first such low-latency EMAC ASIC and FPGA core to achieve ASIL-D safety certification, the highest degree of safety compliance under the ISO-26262 standard. This makes the LLEMAC-1G a smart choice for use with TSN Ethernet for the most life-critical automotive systems, including brakes, airbags, and power steering.

Sourced from partner Fraunhofer IPMS, the LLEMAC-1G core is compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications. It enables high-precision synchronization in TSN networks, with extremely competitive latencies of just six clock cycles for the reception and ten clock cycles for the transmission of packets. The Safety Enhanced version of the core includes an ISO-26262 “ASIL-D Ready” certificate, issued by SGS-TÜV Saar GmbH, as well as the Safety Manual (SAM) and Failure Modes, Effects and Diagnostics Analysis (FMEDA) needed for efficient ASIL-D implementation.

Automotive Ethernet Congress logoVisitors to the 6th Automotive Ethernet Congress this week in Munich can discuss the new core with the Fraunhofer IPMS/CAST automotive networking team in booth 18C.  

The LLEMAC-1G is available now, in synthesizable Verilog source code or as a targeted netlist for Intel, Xilinx, or Lattice FPGA devices. It joins TSN Switched Endpoint, TSN Endpoint, and CAN-to-TSN Gateway cores in CAST’s popular Automotive Interfaces family, which also includes IP for CAN 2.0/FD, LIN, and SENT. These are part of CAST’s broader IP portfolio, including 32- and 8-bit processors; hardware compression/decompression engines for data, images, and video; and numerous other interfaces and peripherals. 

Learn more about CAST’s complete line of IP by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 202.891.8300. 

# # #

 

CAST is a trademark of CAST, Inc. Other trademarks are the property of their respective owners. CAST, Inc., 50 Tice Blvd, Suite 340, Woodcliff Lake, NJ 07677 USA • phone: +1 201.391.8300

 

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