Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit the product pages:

  • TSN-SE TSN Ethernet Switched Endpoint Controller Core
  • TSN-EP TSN Ethernet Endpoint Controller Core

News CAST Adds Switched TSN Endpoint Controller to Time-Sensitive Networking Ethernet IP Cores Family

Enables easy implementation of small, low-power, low-latency TSN Ethernet nodes for daisy-chained or ring networks

Woodcliff Lake, NJ, January 17 2020

Semiconductor intellectual property (IP) provider CAST, Inc. today announced the availability of a new IP core implementing a switched endpoint controller supporting the Time-Sensitive Networking (TSN) Ethernet standards.

The new TSN-SE TSN Ethernet Switched Endpoint Controller IP core integrates hardware stacks for timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav and IEEE 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.1Qbr), and a low-latency Ethernet MAC.

TSN Ring Network with CAST TSN-SE  Switched Endpoint Controller Cores  (diagram based on the IEEE TSN Requirements Specification).

TSN Ring Network with CAST TSN-SE Switched Endpoint Controller Cores (diagram based on the IEEE TSN Requirements Specification).

The company believes the TSN-SE to be one of the smallest and most energy-efficient such cores available, and it features remarkably low latency, implementing nearly every function in hardware. Furthermore, the endpoint controller portion of the core has been proven in multiple industry plugfests, public demos, and customer applications.

“Industrial and automotive systems designers can now build efficient TSN Ethernet ring networks with all the technical features, reliability, performance, easy reusability, and great customer support CAST IP cores are known for,” said CAST CEO Nikos Zervas.

About the TSN-SE Switched Endpoint Controller Core

Sourced from partner Fraunhofer IPMS, the new core builds on the Fraunhofer/CAST team’s market-leading technical and customer experience helping customers integrate TSN Ethernet and other industrial and automotive interfaces.

The highly-competitive core enables high-precision timing synchronization and flexible yet accurate traffic scheduling. Cut-through switching and minimal buffering—even at the Ethernet MAC level—enable extremely low and deterministic input and output latencies. Standard AMBA® interfaces and other features facilitate easy system integration, simplifying the development of time-aware daisy-chained networks.

The TSN-SE is available now, in synthesizable Verilog source code or as a targeted netlist for Intel, Xilinx, or Lattice FPGA devices. It joins TSN Endpoint and CAN-to-TSN Gateway cores in CAST’s popular Automotive Interfaces family, which also includes IP for CAN 2.0/FD, LIN, and SENT.

CAST TSN-SE Switched Endpoint Controller IP Core Block Diagram
Block Diagram for CAST TSN-SE Time-Sensitive Ethernet Switched Endpoint Controller Core 

These are part of CAST’s broader IP portfolio, including 32- and 8-bit processors; hardware compression/decompression engines for data, images, and video; and numerous other interfaces and peripherals. 

Learn more about CAST’s complete line of IP by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 202.891.8300. 

  

  

  

  

  

  

  

CAST is a trademark of CAST, Inc. Other trademarks are the property of their respective owners. CAST, Inc., 50 Tice Blvd, Suite 340, Woodcliff Lake, NJ 07677 USA • phone: +1 201.391.8300

 

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