Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
Automotive Ethernet
TSN Endpoint Controller
CAN-to-TSN Gateway
LIN
LIN Bus Master/Slave
LIN Bus VIP
SENT/SAE J2716
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit the product pages:

  • GZIP-RD-XIL GZIP & GUNZIP Accelerator Reference Design for Xilinx FPGAs
  • ZipAccel-C GZIP/ZLIB/Deflate Data Compression Core
  • ZipAccel-D GUNZIP/ZLIB/Inflate Data Decompression Core
  • GZIP-RD-A10 PCIe GZIP Compression Acceleration Card Reference Design

News Data Compression Accelerators from CAST Now Available on Xilinx Alveo Boards

Reduce bandwidth and storage requirements with standard GZIP/ZLIB/Deflate compression at over 90Gbps on Xilinx Alveo Data Center Accelerator Cards

Woodcliff Lake, NJ, September 27 2019

Semiconductor intellectual property (IP) provider CAST, Inc. today announced that its GZIP/ZLIB/Deflate Compression and Decompression reference designs are now available on Xilinx®Alveo™ Data Center Accelerator Cards. 

Already successfully deployed by multiple customers on Xilinx Kintex® and Virtex® Ultrascale FPGA boards, the GZIP-RD-XIL GZIP & GUNZIP Accelerator Reference Design now running on Xilinx Alveo PCIe cards delivers an unmatched combination of good compression ratio, low latency, and high throughout. As shown in Table 1, data compression at over 90 Gigabits per second (Gbps) is possible with the compression IP running on the mid-range Alveo U200 Card.

Table highlighting good compression rations and high performance for the GZIP Reference Design

Table 1. Representative configurations of the GZIP-RD-XIL reference design running on various Xilinx FPGA boards, with the key statistics of compression ratio (C/R) and performance (Gbps) highlighted. 

The company believes this industry-leading hardware compression combined with the complete Xilinx Alveo ecosystem makes the GZIP-RD-XIL one of the best-available options for reducing bandwidth and storage requirements in data centers and other data-heavy applications.

About the GZIP Accelerator Reference Design 

Block diagram for the GZIP Reference Design on Alveo and other Xilinx FPGA boards

Sourced from partner Sandgate Technologies (www.sandgate.com), the lossless data compression and decompression engines in the reference design comply with the Deflate, GZIP, and ZLIB compression standards. 

The ZipAccel-C Compression IP coreoffers a flexible architecture capable of extremely high throughput and latency as low as a few tens of clock cycles. The ZipAccel-D Decompression IP Coreon average outputs three bytes of decompressed data per clock cycle with a latency of a few tens of clock cycles for blocks coded with static Huffman tables, or under 2,000 cycles for those with dynamic Huffman tables. Instances of the cores can be combined for easy scalability, and they are available for multiple ASIC and FPGA technologies.

The ZipAccel cores are part of CAST’s broad IP portfolio, which includes 32- and 8-bit processors; hardware compression/decompression engines for data, images, and video; automotive and other interfaces and peripherals, and a comprehensive SoC security solution. 

Learn more about the GZIP-RD-XIL GZIP & GUNZIP Accelerator Reference Design on Xilinx Alveo Cards and CAST’s complete line of IP by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 202.891.8300. 

CAST is a trademark of CAST, Inc. ZipAccel is a trademark of Sandgate Technologies. Xilinx, Kintex, and Virtex are registered trademarks and Alveo is a trademark of Xilinx, Inc. Other trademarks are the property of their respective owners.

 

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